Interconnect Parasitics Research Articles

Recent Advance in Non-Krylov Subspace Model Order Reduction of Interconnect Circuits

Model order reduction of interconnect circuits is an important technique to reduce the circuit complexity and improve the efficiency of post-layout verification process in the nanometer VLSI design. Existing works using the Krylov subspace method are very efficient, but the resulting models are less compact and lack global accuracy. Also, existing methods cannot handle interconnect circuits with large input and output ports. Recent advances in reduction techniques using non-Krylov subspace techniques such as truncated balanced realization (TBR) hold some promise to solve these problems. In this paper, we first review the classic TBR-based reduction methods and then present the recent developments in fast TBR-based reduction and techniques such as PMTBR, SBPOR, and ETBR methods. These newly proposed methods try to avoid the expensive computing steps in traditional TBR methods at some cost to accuracy to boost efficiency and scalability, which is critical to reduce large interconnect parasitics modeled as RLCK circuits. The ETBR method can also reduce circuits with massive ports by considering the input signals. We show the pros and cons of each method and compare them on a set of large interconnect circuits, and finally point to some new research directions for this area.

Band-to-Band Tunneling Ballistic Nanowire FET: Circuit-Compatible Device Modeling and Design of Ultra-Low-Power Digital Circuits and Memories

Band-to-band tunneling (BTBT) nanowire FETs have been studied as a possible successor to CMOS FETs. In the literature, it has already been shown that a 1-D p+-i- n+-type semiconductor nanowire governed by a BTBT transport mechanism offers a subthreshold swing lower than the conventional limit of 60 mV/dec while maintaining a reasonable on-state performance. The concept of BTBT nanowire FETs is primitive, and the manufacturing process is nascent. In the absence of a suitable device model and/or a reliable circuit simulator, the evaluation and impact of such novel transistors are difficult to estimate. In this paper, we propose a simple complementary device model for BTBT nanowire FETs suitable for multitransistor circuit simulation and evaluate its performance in the ballistic limit. The device models so developed have been used to simulate a class digital logic circuits and dynamic memories (e.g., DRAM) to analyze their suitability in future very large scale integration design. Circuit level simulations explicitly show that the proposed p+ -i-n+-type BTBT nanowire FETs are well suited for medium throughput (approximately hundreds of kilohertz to a few tens of megahertz) ultra-low-power applications. The standby leakage power in memory and logic circuits has been found to be as low as 10-20 W due to the inherent super cutoff nature of the device. The presence of interconnect parasitics in parallel with intrinsic device capacitance severely limits the performance of digital circuits. The impact of interconnect parasitics on the performance of BTBT nanowire FETs has also been studied.

Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing

Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays. With the component density of these devices, small analog circuits, as well as larger analog systems, can be synthesized and tested in a shorter time and at a lower cost, compared with the full design cycle. However, automated development platforms and computer-aided design tools for these devices are far fewer than the physical synthesis tools for their digital counterparts. One of the major reasons for this is the considerably higher impact of interconnect parasitics on circuit functionality in the analog domain; therefore, performance optimization must be recognized as an indispensable step of the analog physical synthesis flow. Our goal in this brief is to present a physical synthesis framework with an optimization core and an integrated simulation environment for verification of the synthesis results. Although SPICE has been used as the simulation tool for our experiments, there is no dependency on a particular circuit simulator. Our synthesis tool currently accepts SPICE netlists as input and gives priority to user-specified metrics when optimizing the synthesized circuit performance. Experimental results demonstrate the effectiveness of our approach.

De-embedding method for on-wafer RF CMOS inductor measurements

In this work, an accurate de-embedding method for on-wafer RF measurements of CMOS large area devices like the inductors is presented. The method uses distributed and lumped-element models to represent the parasitic elements. The interconnect parasitics are calculated using the transmission line theory. The proposed method is compared to existing de-embedding methods. The validity of the method is checked with the DC resistance value of the interconnects as calculated from the layout and as extracted from measurements, as well as with inductance results of the fabricated inductor, extracted from measurements and from electromagnetic simulations. On-wafer S-parameter measurements have been taken from a test chip up to 20GHz.

A Flexible Microwave De-Embedding Method for On-Wafer Noise Parameter Characterization of MOSFETs

A flexible noise de-embedding method for on-wafer microwave measurements of silicon MOSFETs is presented in this study. We use the open, short, and thru dummy structures to subtract the parasitic effects from the probe pads and interconnects of a fixtured MOS transistor. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate, drain, and source terminals of the MOSFET. The parasitics of the dangling leg in the source terminal are also modeled and taken into account in the noise de-embedding procedure. The MOS transistors and de-embedding dummy structures were fabricated in a standard CMOS process and characterized up to 20 GHz. Compared with the conventional de-embedding methods, the proposed technique is accurate and area-efficient.

Scalable Short-Open-Interconnect S-Parameter De-Embedding Method for On-Wafer Microwave Characterization of Silicon MOSFETs

In this paper, we propose an accurate and scalable S-parameter de-embedding method for RF/microwave on-wafer characterization of silicon MOSFETs. Based on cascade configurations, this method utilizes planar open, short, and thru standards to estimate the effects of surrounding parasitic networks on a MOS transistor. The bulk-shielded open and short standards are used to simulate and de-embed the probe-pad parasitics. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate and drain terminals of the MOSFET. To further eliminate the parasitics of dangling leg in source terminal of the MOSFET, we also introduce the microwave and multi-port network analysis to accomplish the two-port-to-three-port transformation for S -parameters. The MOSFET and its corresponding de-embedding standards were fabricated in a standard CMOS process and characterized up to 40GHz. The scalability of the open, short, and thru standards is demonstrated and the performance of the proposed de-embedding procedure is validated by comparison with several de-embedding techniques.

Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers

In this brief, a design strategy to minimize the delay of high-fan-in CMOS multiplexers (MUXes) based on the heterogeneous-tree approach is proposed. A preliminary circuit analysis is carried out that takes interconnect parasitics into account, and analytical design criteria are then derived by assuming that the MUX switches are made up of pass transistors or transmission gates, as is often done in practical cases. The design criteria turn out to be very simple (even more than those in [1] which did not consider the effect of interconnects) and independent of the adopted technology. In addition, an approximate delay expression is given to predict the achievable speed performance before actually carrying out the optimized design. The results are validated through post-layout simulations on a 90-nm CMOS process.

A low-power/low-noise readout circuit for integrated capacitive sensors

A switched-capacitor integrated system is presented in this work that attains sub-fF measurement resolution in integrated capacitive sensors, with 1.5-kHz bandwidth and 50-muW average power consumption in continuous function mode. The proposed design employs a pair of nonoverlapping clocks and an operational transconductance amplifier (OTA) that can be made as simple as a basic differential pair. The system exhibits 0.8% linearity error and 0.01 fF/degC temperature drift. It is appropriate for differential, absolute, and ratiometric capacitance measurements, and shows robustness against interconnection parasitics, transistor dimensional mismatch, and process variations, which are an important feature in the case of sensor-die CMOS postprocessing

Neural-network-based parasitic modeling and extraction verification for RF/millimeter-wave integrated circuit design

This paper reports an interconnect modeling approach for RF and millimeter-wave integrated circuits (ICs) using neural network models and a novel parasitic extraction verification procedure using automatically generated test structures. The effects of the parasitics in RF/millimeter-wave ICs are investigated with special focus on the parasitic inductances, since they are not evaluated by most of the commercially available extraction tools. State-of-the-art silicon-based multilayer RF process parameters are utilized to extract the resistive, the capacitive, and the inductive components of the layout interconnects. Neural network models are developed using electromagnetic (EM) simulation results of a set of passive interconnect structures. In addition, an automated layout generation methodology is used for the verification of the parasitic extraction methodologies. The proposed verification approach is demonstrated using automatically generated passive test structures and ring oscillators. The effects of parasitics are also investigated in voltage-controlled oscillators (VCOs) and amplifiers for millimeter-wave applications, and the neural models are verified using 30-GHz VCO measurement results. Hence, we present a complete modeling report of layout interconnect parasitics in RF/millimeter-wave integrated circuits as well as a novel verification procedure to validate non-EM analytical or neural models

Passive and heterogeneous integration towards a Si-based System-in-Package concept

Recently Philips launched their first highly integrated cellular RF-transceiver systems using a new Si-based System-in-Package (SiP) technology. This technology utilizes back-end processing to integrate passive components onto a Si-substrate that serves as a platform for heterogeneous integration with active dies, MEMS dies, etc. As an example, a transceiver IC is flip-chip mounted onto this passive component substrate, thus minimizing interconnect parasitics and footprint area. Next, this sub-assembly is flipped back into a standard single IC-sized lead frame package. This paper reports on such Si-based SiP transceiver modules and the underlying technologies. Here, the passive die is made by the so-called PICS ( Passive Integration Connecting Substrate) technology that integrates passive components on one die, such as high-Q inductors, resistors, accurate MIM capacitors and, in particular, high-density (∼ 20–30 nF/mm 2) MOS ‘trench’ capacitors for decoupling. These MOS capacitors integrated in RF power amplifiers showed superior signal stability compared to discrete ceramic capacitors. Ultralow-loss factors were measured: series inductance ESL < 40 pH and resistance ESR < 150 mΩ, combined with superior dielectric breakdown voltage (30 V), low leakage (< 1 nA/mm 2 at 22 V) and long lifetime of 10 years at 100 °C and 10 V).

Integrated Phased Array Systems in Silicon

Silicon offers a new set of possibilities and challenges for RF, microwave, and millimeter-wave applications. While the high cutoff frequencies of the SiGe heterojunction bipolar transistors and the ever-shrinking feature sizes of MOSFETs hold a lot of promise, new design techniques need to be devised to deal with the realities of these technologies, such as low breakdown voltages, lossy substrates, low-Q passives, long interconnect parasitics, and high-frequency coupling issues. As an example of complete system integration in silicon, this paper presents the first fully integrated 24-GHz eight-element phased array receiver in 0.18-/spl mu/m silicon-germanium and the first fully integrated 24-GHz four-element phased array transmitter with integrated power amplifiers in 0.18-/spl mu/m CMOS. The transmitter and receiver are capable of beam forming and can be used for communication, ranging, positioning, and sensing applications.

A shield-based three-port de-embedding method for microwave on-wafer characterization of deep-submicrometer silicon MOSFETs

A general three-port S-parameter de-embedding method using shield-based test structures for microwave on-wafer characterization is presented in this paper. This method does not require any physical equivalent-circuit assumption for the surrounding parasitics of a device-under-test. We use one open and three thru dummy devices to remove the parasitic components connected to the gate, drain, and source terminals of a MOSFET. By shielding the lossy silicon substrate, the cross-coupling from port to port can be significantly mitigated, and thus, the parasitics of probe pads and interconnects at each port can be separately subtracted. The MOS transistor and its corresponding dummy structures fabricated in a 0.18-/spl mu/m CMOS process were characterized up to 20 GHz. Compared with the two-port cascade-based de-embedding method, the proposed three-port de-embedding procedure can further eliminate the parasitics associated with the dangling leg in the source terminal. The impacts of the accuracy of the de-embedding technique on device modeling and simulation are also discussed.

Three-dimensional system-in-package using stacked silicon platform technology

In this paper, a novel method of fabricating three-dimensional (3-D) system-in-package (SiP) using a silicon carrier that can integrate known good dice with an integrated cooling solution is presented. The backbone of this stacked module is the fabrication of a silicon carrier with through-hole conductive interconnects. The design, process, and assembly to fabricate silicon through-hole interconnect using a wet silicon etching method is discussed in this paper. The process optimization to fabricate silicon carriers with solder through-hole interconnect within the design tolerance has been achieved. The design and modeling methodology to optimize the package in terms of electrical aspects of the stacked module is carried out to achieve less interconnect parasitics. An integrated cooling solution for 3-D stacked modules using single-phase and two-phase cooling solutions is also demonstrated for high-power applications. Known good thin flip-chip devices with daisy chain are fabricated and attached to the silicon carrier by flip-chip processes making it a known good carrier after electrical testing. Individual known good carriers are vertically integrated to form 3-D SiP.

A Cascade Open-Short-Thru (COST) De-Embedding Method for Microwave On-Wafer Characterization and Automatic Measurement

SUMMARY In this study, a cascade open-short-thru (COST) deembedding procedure is proposed for the first time for on-wafer device characterization in the RF/microwave frequency regime. This technique utilizes the “open” and “short” dummy structures to de-embed the probepad parasitics of a device-under-test (DUT). Furthermore, to accurately estimate the input/output interconnect parasitics, including the resistive, inductive, capacitive, and conductive components, the “thru” dummy device has been characterized after probe-pad de-embedding. With the combination of transmission-line theory and cascade-configuration concept, this method can efficiently generate the scalable and repeatable interconnect parameters to completely eliminate the redundant parasitics of the active/passive DUTs of various device sizes and interconnect dimensions. Consequently, this method is very suitable for the on-wafer automatic measurement.

High-bandwidth balanced photoreceiver suitable for 40-gb/s RZ-DPSK modulation formats

A novel fully packaged balanced photoreceiver designed for 40-Gb/s differential phase shift keying (DPSK) applications at 1.55-/spl mu/m wavelength is presented. Based on InP : Fe substrate, two waveguide-integrated photodiodes with spot size converters are monolithically integrated with a distributed amplifier. This configuration leads to a high symmetry of the two optical inputs and avoids interconnection parasitics. The RF output of the photoreceiver is dc-coupled, but the design enables an interfacing to subsequent electronics without external bias-tee by using a negative bias supply at the source terminal of the integrated amplifier. A reduction of system costs and required space will be obtained by this concept. Mounted in a butterfly package, a 3-dB cutoff frequency of 42 GHz is achieved. Return-to-zero (RZ)-DPSK experiments exhibit excellent operation of the balanced photoreceiver over a large dynamic range of optical input power up to +10 dBm. The high-power capability and the clear eye opening at low input power demonstrates the suitability for high performance core and metro systems.

Development of G-Helix Structure as Off-Chip Interconnect

Microsystem packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. G-Helix, an electroplated compliant wafer-level chip-to-substrate interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the G-Helix interconnect is similar to conventional IC fabrication process and is based on electroplating and photolithography. G-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of an area-arrayed G-Helix interconnects. The geometry effect on the mechanical compliance and electrical parasitics of G-Helix interconnects have been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance may not have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done. Furthermore, reliability of the optimized G-helix interconnects in a silicon-on-organic substrate assembly has been assessed, which includes the package weight and thermo-mechanical analysis. The pitch size effect on the electrical and mechanical performance of G-Helix interconnects has also been studied.

Parasitics Extraction With Multipole Refinement

Modern chip design pushes the performance of a given technology to its limits, therefore, it is necessary to find increasingly more accurate models for interconnect parasitics. The growing complexity of today's integrated systems, however, makes fast analysis crucial as well. We present a novel hierarchical potential evaluation technique which is able to represent detailed near-field and global far-field couplings with equal accuracy and efficiency by combining the best features of known hierarchical approaches in this field.

Polycrystalline silicon-germanium films for integrated microsystems

Two approaches were demonstrated for fabricating microstructures after completion of CMOS circuits with aluminum metallization. The first approach employed n-type poly-Ge deposited at 400/spl deg/C as a structural material with an SiO/sub 2/ sacrificial layer and an HF release. The CMOS circuits were protected from the release etchant with an amorphous Si layer. Clamped-clamped lateral resonator test structures had quality factors in vacuum as high as /spl sim/30000. Following a 500/spl deg/C, 30 s RTA the poly-Ge stress was 200 MPa (tensile) and the resistivity was 5.3 m/spl Omega/-cm. In the second integration approach, p-type poly-Si/sub 0.35/Ge/sub 0.65/ deposited at 450/spl deg/C was the structural material with poly-Ge as the sacrificial material and H/sub 2/O/sub 2/ as the release etchant. The H/sub 2/O/sub 2/ did not significantly etch the p-type poly-SiGe structural layer and no protection of the underlying CMOS layers was needed. For the first time, the fabrication of LPCVD surface microstructures directly on top of standard electronics was demonstrated, providing dramatic reductions in both MEMS-CMOS interconnect parasitics and device area. A folded flexure lateral resonator had a quality factor in vacuum as high as /spl sim/15000. No stress or dopant-activation anneal was needed, since the in situ boron-doped poly-SiGe was found to have an as-deposited stress of only -10 MPa (compressive) and a resistivity of only 1.8 m/spl Omega/-cm.

A 7 GHz 1.5-V Dual-Modulus Prescaler in 0.18 μm Copper-CMOS Technology

A dual-modulus prescaler using True-Single-Phase-Clock (TSPC) logic is implemented in a 0.18 mm copper CMOS technology. With careful design and optimization the prescaler is able to operate at frequency up to 7.14 GHz at 1.5 V supply voltage. The high-speed operation is attributed to the adoption of the TSPC dynamic logic, and the all copper interconnect CMOS process which has much less interconnect parasitics than conventional aluminum technology. The design facilitates the implementation of a fully integrated RF CMOS phase-locked loop for applications in the 5.8 GHz ISM band such as wireless LAN.

An analysis of the wire-load model uncertainty problem

Traditional integrated-circuit (IC) design methodologies have used wire-load models during logic synthesis to estimate the expected impact of the metal wiring on the gate delays. These models are based on wire-length statistics from legacy designs to facilitate a top-down IC design flow process. Recently, there has been increased concern regarding the efficacy of wire-load models as deep-submicrometer (DSM) interconnect parasitics begin to dominate the delay of digital IC logic gates. Some technology projections (Sylvester and Keutzer, 1998) have suggested that wire-load models will remain effective to block sizes on the order of 50 000 gates. This suggests that existing top-down synthesis methodologies will not have to be changed substantially since this is approximately the maximum size for which logic synthesis is effective. However, our analyses on production designs show that the problem is not quite so straightforward and the efficacy of synthesis using wire-load models depends upon technology data as well as specific characteristics of the design and the granularity of available physical information. We analyze these effects and dependencies in detail in this paper and draw some conclusions regarding the future challenges associated with top-down IC design and block synthesis, in particular, in the DSM design era.