Abstract

Ferroelectric tunnel junction (FTJ) based crossbar array is a promising candidate for the implementation of low-power and area-efficient neuro-inspired computing. In this paper, we fabricated and measured a 10 nm thick Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FTJ with > 100 on/off ratio and multi-state storage. We found out that the current density of this FTJ is too low for sensing circuitry to distinguish reliably and efficiently. To overcome the low current of FTJs, we suggested using an ultra-thin 1 nm FTJ and employing the concept of stacked capacitors from modern DRAM processes. Following this idea, we further projected a 1 nm thick stacked FTJ and ran the crossbar arrays in the 20 nm node, which shows a desirable summed current level on the order of 10 μA. To model a realistic data pattern of on-state and off-state devices in a 1024 × 1024 array, we mapped quantized weights from a fully connected layer of a deep neural network to the memory cells. The current accuracy and delay are evaluated using array-level SPICE simulations with the consideration of interconnect parasitics. The overall results suggest that FTJ crossbar array is of the potential for realizing neuro-inspired computing.

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