MOSFET Research Articles

Second generation current conveyor based capacitorless floating memristor emulator

AbstractThis article offers a novel flux controlled floating memristor emulator based on second‐generation current conveyor (CCII). The floating memristor is designed using two CCIIs, one resistor, and one PMOS transistor. The presented memristor emulator does not need external capacitance. The proposed designed circuit exhibits pinch hysteresis loops in voltage–current plane up to 2 GHz frequency. The performance of the circuit under consideration is evaluated using 180 nm CMOS technology parameter by the SPICE simulator. The circuit requires a DC power supply of ±1.2 V and exhibits a power consumption of 0.766 mW. Furthermore, the resilience of the planned circuit is assessed by examining process corner fluctuation, supply voltage variation, temperature variation, and transistor size variations. In addition, a Schmitt trigger circuit and high order filters based on designed memristor are used to confirm the operation of the proposed design at high and low frequency, respectively.

An Ultra-Low-Voltage Approach to Accurately Set the Quiescent Current of Digital Standard Cells Used for Analog Design and Its Application on an Inverter-Based Operational Transconductance Amplifier

An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA.

Statistical analysis of vertically stacked nanosheet complementary FET based on polycrystalline silicon with multiple grain boundaries

In this study, a complementary field-effect transistor (CFET) based on a polycrystalline silicon (poly-Si) stacked-nanosheet (NS) structure with a grain boundary (GB) is designed and analyzed using a technology computer-aided design (TCAD) simulation. The advantage of the CFET using a poly-Si is that the active cell region can be reduced by 50 % because the p-type transistors are vertically stacked on the n-type transistors. In addition, it is possible to replace the conventional CMOS process and fabricate a three-dimensional vertically stacked structure at a low cost. To consider the effect of the GB in poly-Si, we assumed that there is a single GB at the center of the body region. By optimizing the geometrical parameters of the proposed CFET, the transfer characteristics of the NMOS and PMOS transistors, such as the threshold voltage (Vth), on current (Ion), off current (Ioff), and subthreshold swing (SS), are symmetrical. The proposed CFET demonstrated a superior logic performance of NML = 0.299 V and NMH = 0.297 V at an operation voltage of VDD = 0.65 V. To consider random GBs in the poly-Si, we assumed that five GBs existed in the proposed CFET, and the variation in CMOS logic inverter characteristics are statistically analyzed. As a result, the RSDs for Vm of the NMOS and PMOS transistors are 2.067 % and 0.293 %, and the RSDs of the pull-down delay time (tpHL) and pull-up delay time (tpLH) are 5.320 % and 3.244 %, respectively. An acceptor-like traps with high trap density are dominant in the proposed CFET, and this trend is similar across the 1024 samples. Nevertheless, most of the differences are within 5 % and the proposed CFET exhibited stability against GBs and the potential to replace the conventional CMOS logic inverters.

Effect of Electronic Properties of Si1-xGex and SiC Semiconductors on the Electrical Behavior of MOS Transistors

In this paper, the electrical performance of Metal-Oxide-Semiconductor MOS transistors in Si1-xGex and SiC technologies have been studied by BSIM3v3 model. In which the output charac- teristic ID=f(VDS), transfer characteristic ID=f(VGS) and ION-IOFF currents of the MOS(Si1-xGex) transis- tors have been investigated and the results so obtained are compared with the MOS(SiC) transistors, using 130 nm technology and OrCAD PSpice software. This study allowed to know the extent to which the electrical behavior of transistors is affected by the most important electronic properties of semiconductors, and the simulation results showed that the above transistors work properly in a regime under a threshold voltage of about 1.2 V. They can be used in low voltage and low power microelectronics by controlling the germanium x fraction and the polytypes of MOS(Si1-xGex) and MOS(SiC) transistors respectively.

Применение бентонитовой глины в качестве гидроизоляционного материала

Purpose: analytical study of usability bentonite is a natural mineral with high waterproofing and adsorption properties in various fields. Methods: methods of comparative analysis, synthesis, generalization, analogy were used. Results: this article examines various applications of bentonite, allowing to position bentonite as a universal material, which is widely used in various industries due to its unique properties. The advantages of bentonite over other waterproofing materials are noted, including environmental friendliness, durability, efficiency and economy. The properties of bentonite clay have been studied, the ability of which to swell and create a waterproofing barrier in contact with water makes it an effective material for protection against moisture. It is indicated that the high frost resistance of bentonite is ensured due to the complex structure of the material consisting of metal oxide atoms and silicon atoms, which form a dense structure. The interlayer space in which the exchange cations are concentrated is the physical and physicochemical basis for the sorption activity of bentonite clay rocks. Bentonite has been found to be of value in its self-healing properties, as is the case when used at negative temperatures. This is due to its molecular structure. The microscopic particles that make up bentonite have a negative charge, they are able to adsorb water molecules. Practical significance: waterproofing works are carried out in many areas of construction. However, bentonite materials are not widely used. In this aspect, the article describes in detail such waterproofing materials as bentonite mats, clay lock, injectable bentonite waterproofing. The authors believe that the demand for the use of bentonite as a reliable and promising means of waterproofing in the construction industry will increase.

High-performance anti-series diode ring amplifier for switched capacitor circuits

Ring amplifiers enable efficient amplification with less power consumption. These are characterized by fairly power requirements, and innate rail-to-rail output swing and are robust against PVT variations. In this paper, we are presenting an improved self-biased anti-series diode-based ring amplifier (ASD-RAMP) design, implemented on 45-nm CMOS technology. The design uses two diode-connected PMOS transistors that are connected in an anti-series manner to generate a large resistance because of which a high dead-zone voltage is generated. The ASD-RAMP has a settling time of only 4.05 ns, which is nearly half of the conventional self-biased ring amplifier (CSB-RAMP). In comparison to CSB-RAMP, the proposed ASD-RAMP improves the dead-zone voltage by 1.1× while requiring 6.76% less power. The circuit is durable and suitable for high-performance applications since it exhibits great resilience to PVT variations in addition to the improved dead zone voltage and reduced settling time.

A 64 × 128 3D-Stacked SPAD Image Sensor for Low-Light Imaging.

Low-light imaging capabilities are in urgent demand in many fields, such as security surveillance, night-time autonomous driving, wilderness rescue, and environmental monitoring. The excellent performance of SPAD devices gives them significant potential for applications in low-light imaging. This article presents a 64 (rows) × 128 (columns) SPAD image sensor designed for low-light imaging. The chip utilizes a three-dimensional stacking architecture and microlens technology, combined with compact gated pixel circuits designed with thick-gate MOS transistors, which further enhance the SPAD's photosensitivity. The configurable digital control circuit allows for the adjustment of exposure time, enabling the sensor to adapt to different lighting conditions. The chip exhibits very low dark noise levels, with an average DCR of 41.5 cps at 2.4 V excess bias voltage. Additionally, it employs a denoising algorithm specifically developed for the SPAD image sensor, achieving two-dimensional grayscale imaging under 6 × 10-4 lux illumination conditions, demonstrating excellent low-light imaging capabilities. The chip designed in this paper fully leverages the performance advantages of SPAD image sensors and holds promise for applications in various fields requiring low-light imaging capabilities.

A Novel Dung Beetle Optimization Approach for Automatic CMOS Analog Circuit Design

The main objective of the automated circuit sizing technique is to deal with the challenges of design tradeoffs in analog circuit design with improved accuracy and efficacy. Analog circuit design represents a multi-objective optimization challenge, where designers must properly balance various performance factors such as input and output impedance, power dissipation, area, unity-gain bandwidth, slew rate, and open-loop DC gain. Traditional design equations provide a sizing of differential amplifier MOS transistors, further optimization can be achieved through the application of meta-heuristic search techniques. Meta-heuristic search techniques can be used as local optimizers in a smaller search area to improve the optimization of design parameters. The differential amplifier circuit with current mirror load is optimized through the application of the Dung Beetle Optimization (DBO) algorithm. By using an evolutionary algorithm called DBO, all the required parameters were achieved with the least amount of transistor area and power dissipation when compared to the results of the Seeker Optimization Algorithm (SOA), Opposition based Harmony Search Algorithm (OHS), craziness-based particle swarm optimization (CRPSO), and Cuckoo Search (CS) algorithms.

An improved small signal model of a mos transistor in millimeter wave band considering longitudinal distributed effects

An improved small signal model of a mos transistor in millimeter wave band considering longitudinal distributed effects

Strain Driven Electrical Bandgap Tuning of Atomically Thin WSe2

AbstractTuning electrical properties of 2D materials through mechanical strain has predominantly focused on n‐type 2D materials like MoS2 and WS2, while p‐type 2D materials such as WSe2 remain relatively unexplored. Here, the impact of controlled mechanical strain on the electron transport characteristics of both mono and bi‐layer WSe2 is studied. Through coupling atomic force microscopy (AFM) nanoindentation techniques and conductive AFM, the ability to finely tune the electronic band structure of WSe2 is demonstrated. The research offers valuable mechanistic insights into understanding how WSe2's electronic properties respond to mechanical strain, a critical prerequisite for the development of flexible photoelectronic devices. It is also observed that under high pressure, the AFM tip/monolayer WSe2/metal substrate junction transitions from Schottky to Ohmic contact, attributed to significant charge injection from the substrate to the WSe2. These findings are significant for designing efficient metal/semiconductor contact in thin and flexible PMOS (p‐type Metal–Oxide–Semiconductor) devices.

A CMOS Inverter-Based Active Feedback Transimpedance Amplifier

This paper presents an inverter-based active feedback transimpedance amplifier (IAF-TIA), in which an active feedback is applied to a voltage-mode inverter-based TIA, and therefore, the controlled positive regeneration process enables the proposed IAF-TIA to achieve the limiting operations for input currents greater than 100 μApp. However, the active inverter feedback mechanism might be prone to instability, hence mandating a very careful optimization of the loop gain. For this purpose, a diode-connected NMOS transistor is employed as a switch in the feedback path with its gate connected to the input, which helps not only to mitigate the corresponding issue but also to accommodate large input currents up to 1.5 mApp. The proposed IAF-TIA implemented in a standard 180 nm CMOS process demonstrates a 70.5 dBΩ transimpedance gain, 1.21 GHz bandwidth, 4.3 pA/Hz noise current spectral density, 63.5 dB input dynamic range, and 23.6 mW power dissipation from a single 1.8 V supply. The chip core occupies an area of 180 × 50 μm2, including an on-chip P+/N-well/Deep N-well avalanche photodiode as an optical detector.

Impact Produced by Recrystallization of Mechanically Destroyed Layer on Planar Side of Silicon Wafer Upon Electrical Parameters of CMOS Microcircuits

The influence of recrystallization of a mechanically damaged layer on the working side of a silicon wafer using rapid heat treatment (1000 °C, 20 s) on the electrical parameters of complementary metal-oxide-semiconductor microcircuits has been established. The analyzed characteristics of n- and p-channel transistors were selected: drain current from the gate voltage when diode-connected; output characteristics at various gate voltages; drain current from the drain voltage without applying potential to the gate; percentage of yield of suitable products. These parameters were compared with microcircuits manufactured using standard technology. Analysis of the results showed that rapid thermal treatment of the original silicon wafers can significantly improve the above characteristics of n-channel metal-oxide-semiconductor ( n-MOS) and p-channel metal-oxide-semiconductor (p-MOS) transistors by reducing the fixed charge in gate dielectric obtained by pyrogenic oxidation of silicon. This makes it possible to improve the quality of manufactured complementary metal-oxide-semiconductor microcircuits and increase the percentage of yield of suitable products from 74.38 to 77.53 %.

Design and High Performance Evaluation of a Low Power Bit-Line SRAM PMOS Biased Sense Amplifier

Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters. Key Words: Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.

Improved NO2 Sensing Performance of Ternary Nanocomposites Based on Au-doped Co3O4/CuO

To enhance the poor sensing capabilities of traditional p-type metal oxide semiconductor sensors, a novel gas sensor was designed with Co3O4/CuO heterostructure modified by glutathione (GSH)-reduced gold (Au), which was characterized by different analyses. The experiments showed that the 0.5[Formula: see text]wt.% Au–Co3O4/CuO gas sensor exhibited excellent sensing performance with a response value of up to 28.3 for 3[Formula: see text]ppm NO2 at a relatively low operating temperature ([Formula: see text]C). Besides, it demonstrated a linear relationship between detection concentration and response value, displayed good selectivity for NO2, showcased stability and exhibited repeatability. Moreover, the sensor revealed the ability to resist humidity at the optimal temperature. Finally, we proposed a gas sensing mechanism to explain the enhanced NO2 detection performance of the sensor, attributed to the heterojunction structure between Co3O4/CuO and the catalytic properties of Au. This led to an increase in adsorbed oxygen, as confirmed by XPS characterization. Therefore, the 0.5[Formula: see text]wt.% Au–Co3O4/CuO ternary nanocomposite gas sensor is deemed to be a highly effective sensing material that can be utilized to detect NO2 gas in real-life applications.

An ultra‐low‐power low‐noise amplifier using a combination of current reuse and self‐forward body bias techniques for biomedical applications

SummaryLow‐power low noise amplifiers (LNAs) are critical block in the radio frequency (RF) front‐end of medical device radiocommunications service (MedRadio) receivers for amplifying weak received signals while introducing minimal noise. Despite the inherently low transconductance of MOS transistors, it is possible to achieve low noise, high gain, and good linearity in low power LNAs. This paper presents a combination of techniques to realize an ultra‐low‐power LNA with a compact size and high performance. The proposed LNA utilizes multiple gm‐boosting and self‐forward body bias techniques, with certain transistors operating in weak inversion. Additionally, the Multi‐Objective Inclined Planes System Optimization algorithm is employed to determine the optimal values of the circuit components, thereby achieving the best compromise among the various performance parameters. The proposed LNA with buffer is designed and simulated using an 180 nm CMOS process over the frequency band of 0.3–1 GHz. Simulated results show that the proposed LNA achieves a gain of 19.6 dB, a noise figure of 5.1 dB, good input matching (S11 < −10 dB), and a third‐order intermodulation intercept point (IIP3) of 3.8 dBm. Additionally, it consumes 320 μW (without buffer) from a 1 V power supply, and the chip area is 235 μm × 372 μm. The simulated results demonstrate that the proposed ultra‐low power LNA is a promising candidate for biomedical applications.

CMOS operational amplifier design for industrial and biopotential applications: Comprehensive review and circuit implementation

This paper provides a detailed exploration of CMOS operational amplifiers (Op-Amps) aimed at enhancing understanding of their development, design, and application. To achieve this, a comprehensive examination of the common characteristics, parameters, and bibliographic reviews of Op-Amps, distinguishing among various chosen operational amplifiers. A comprehensive bibliographic review of the operational amplifier's keywords between 2008 and 2018 has also been conducted. A bibliometric analysis of 4997 documents from the Web of Science (WOS) Collection is conducted using VOSviewer software. Furthermore, an analysis and comparison of these Op-Amps across functional aspects relevant to industrial and biomedical applications, emphasising the salient characteristics of each technique. After the survey, a novel Op-Amp design is proposed, incorporating a differential amplifier at the first stage, along with a compensating capacitor and a high gain stage. The biasing circuitry is replaced with an active load resistor (MOS transistor), simplifying layout design, and reducing the amplifier's area and power consumption compared to traditional two-stage designs. The power source for this design is 3.3 V. This designed operational amplifier achieved a gain of 62.9449 dB, a high CMRR of 92.8079 dB, and a unity gain bandwidth of 33 MHz, and the optimised layout area is 0.001476 μm2. The proposed circuit was designed and simulated utilising the Cadence Virtuoso 180 nm CMOS process. The simulation results show that the desired criteria have been met. Additionally, the challenges and future possibilities in analog circuits, laying the groundwork for research in both analogue and digital circuits to tackle complex real-world issues have been addressed.

Thermoelectric Performance of Hybrid Inorganic/Organic Composites Based on PEDOT:PSS/Tin(II) Oxide.

PSS(poly(3,4-ethylenedioxylthiophene):poly(styrenesulfonate))-based composites often exhibit remarkable characteristics regarding high electrical conductivity and great processability, being a suitable candidate for thermoelectric (TE) applications. To increase its performance, PEDOT:PSS is commonly blended with scarce and toxic inorganic compounds based on Se, Te or Bi. In this work we propose the use of one p-type metal oxide semiconductor (MOs): tin(II) oxide (SnO), motivated by its abundance and low toxicity. Hybrid PEDOT:PSS/SnO composites were obtained by firstly blending Ethylene glycol (EG) with PEDOT:PSS and then by adding p-type SnO, previously synthesized by a chemical route. The mixture was deposited via spin-coating onto glass substrates. The Power Factor (PF) of the composites increased by a factor of 300 with the combined EG/SnO composition.

Design and Analysis of Low-Power and Area-Efficient Master-Slave Flip-Flop

In this paper, a novel master-slave flip-flop is designed that incorporates 15 transistors and a single-phase clock, employing topological and adaptive coupling methods. The proposed flip-flop circuit (PFC) is more efficient than other logic-structured flip-flops. PFC is designed using a 45 nm Complementary Metal Oxide Semiconductor (CMOS) technology node. Notably, the PFC exhibits an impressive 34.18%, 42.92%, 39.71%, 44.39%, and 46.91% improvement in average power consumption compared to the adaptive data track flip-flop (ADTFF), Hybrid Flip-Flop (HFF),18-transistor single-phase clocked (18TSPC), Logic Structured Reduction Flip-Flop (LSRFF), and Topologically compressed flip-flop (TCFF). It also improved the C to Q delay, power delay product (PDP). Monte Carlo simulations of average power and C to Q delay have been performed for 1000 samples. By reducing the number of PMOS transistors, the total area of the PFC is minimized. PFC operates effectively within a clock frequency range of up to 1 GHz.

Updates on Impact Ionisation Triggering of Thyristors

High voltage (HV) generators are used in multiple industrial and scientific facilities. Recent publications have demonstrated that triggering industrial thyristors (relatively slow switching devices) in overvoltage mode, also called impact ionization mode, significantly enhances their dU/dt and dI/dt characteristics. This novel triggering methodology necessitates the application of substantial overvoltage between the thyristor’s anode and cathode, delivered with a swift slew rate exceeding 1 kV/ns. The adoption of compact pulse generators constructed from commercially available off-the-shelf components (COTS) opens up avenues for deploying this technology across various domains, including the implementation of high-speed kicker generators in particle accelerators. In our methodology, we employed commercially available high-voltage SiC MOSFETs along with a custom-designed fast gate driver. This driver was conceptualized based on the recent development of gate boosting techniques, featuring a driving voltage exceeding 600 V. The gate driver for these MOSFETs comprises three key components: a level-shifter with NMOS and PMOS transistors, a compact Marx generator with two avalanche transistors, and a GaN HEMT in a high input and low output impedance configuration. The proposed gate-boosting driver achieves a slew rate exceeding 1 kV/ns for the driving pulse. Furthermore, we demonstrate that with this driver, a 1.7 kV rated SiC MOSFET can produce an output pulse of 1.45 kV and a maximum slew rate of ≈2.5 kV/ns. This gate-boosting driver aims to minimize commutation times, achieves a slew rate of over 1 kV/ns, and handle higher loads, making it ideal for impact ionization triggering of industrial thyristors.

From interface effect to bulk effect: Probing the capacitive coupling enhancement mechanism to achieve high performance DC droplet-based nanogenerator

The DC droplet-based nanogenerator (DNG) technology has opened up a new avenue for high-entropy water energy harvesting. However, the conventional DC DNG relies on the interface effect to generate a limited surface charge density, which severely restricts its electrical performance. Here, inspired by the MOS transistors, a novel total current DNG (TC-DNG) platform with back-gate modulation structure is developed, successfully realizing the transform from interface effect to bulk effect. By using the rationally patterned DNG as triboelectric probe, an intriguing capacitive coupling enhancement mechanism is discovered. With such a mechanism, the nanogenerator could employ both the capacitive coupling effect of the back-gate electrode and the self-exciting effect of droplet charge-shuttles to achieve a significantly enhanced performance in both charge transfer and voltage output. As a result, this TC-DNG provides a transferred charge of 30 nC per droplet and an output voltage of 800 V and is capable of illuminating 480 high-brightness LEDs without using any power management circuit. In addition, this TC-DNG could easily adapt to a wide range of application scenarios owing to the interchangeability of the back-gate material. This work could inspire further innovations in energy transfer mechanism and harvesting technology at the liquid-solid interface.