A Novel Dung Beetle Optimization Approach for Automatic CMOS Analog Circuit Design

Abstract

The main objective of the automated circuit sizing technique is to deal with the challenges of design tradeoffs in analog circuit design with improved accuracy and efficacy. Analog circuit design represents a multi-objective optimization challenge, where designers must properly balance various performance factors such as input and output impedance, power dissipation, area, unity-gain bandwidth, slew rate, and open-loop DC gain. Traditional design equations provide a sizing of differential amplifier MOS transistors, further optimization can be achieved through the application of meta-heuristic search techniques. Meta-heuristic search techniques can be used as local optimizers in a smaller search area to improve the optimization of design parameters. The differential amplifier circuit with current mirror load is optimized through the application of the Dung Beetle Optimization (DBO) algorithm. By using an evolutionary algorithm called DBO, all the required parameters were achieved with the least amount of transistor area and power dissipation when compared to the results of the Seeker Optimization Algorithm (SOA), Opposition based Harmony Search Algorithm (OHS), craziness-based particle swarm optimization (CRPSO), and Cuckoo Search (CS) algorithms.