Statistical analysis of vertically stacked nanosheet complementary FET based on polycrystalline silicon with multiple grain boundaries

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In this study, a complementary field-effect transistor (CFET) based on a polycrystalline silicon (poly-Si) stacked-nanosheet (NS) structure with a grain boundary (GB) is designed and analyzed using a technology computer-aided design (TCAD) simulation. The advantage of the CFET using a poly-Si is that the active cell region can be reduced by 50 % because the p-type transistors are vertically stacked on the n-type transistors. In addition, it is possible to replace the conventional CMOS process and fabricate a three-dimensional vertically stacked structure at a low cost. To consider the effect of the GB in poly-Si, we assumed that there is a single GB at the center of the body region. By optimizing the geometrical parameters of the proposed CFET, the transfer characteristics of the NMOS and PMOS transistors, such as the threshold voltage (Vth), on current (Ion), off current (Ioff), and subthreshold swing (SS), are symmetrical. The proposed CFET demonstrated a superior logic performance of NML = 0.299 V and NMH = 0.297 V at an operation voltage of VDD = 0.65 V. To consider random GBs in the poly-Si, we assumed that five GBs existed in the proposed CFET, and the variation in CMOS logic inverter characteristics are statistically analyzed. As a result, the RSDs for Vm of the NMOS and PMOS transistors are 2.067 % and 0.293 %, and the RSDs of the pull-down delay time (tpHL) and pull-up delay time (tpLH) are 5.320 % and 3.244 %, respectively. An acceptor-like traps with high trap density are dominant in the proposed CFET, and this trend is similar across the 1024 samples. Nevertheless, most of the differences are within 5 % and the proposed CFET exhibited stability against GBs and the potential to replace the conventional CMOS logic inverters.