Input-referred Noise Research Articles

A CMOS Microelectrode Array System With Reconfigurable Sub-Array Multiplexing Architecture Integrating 24,320 Electrodes and 380 Readout Channels.

This article presents a CMOS microelectrode array (MEA) system with a reconfigurable sub-array multiplexing architecture using the time-division multiplexing (TDM) technique. The system consists of 24,320 TiN electrodes with 17.7 μm-pitch pixels and 380 column-parallel readout channels including a low-noise amplifier, a programmable gain amplifier, and a 10-b successive approximation register analog to digital converter. Readout channels are placed outside the pixel for high spatial resolution, and a flexible structure to acquire neural signals from electrodes selected by configuring in-pixel memory is realized. In this structure, a single channel can handle 8 to 32 electrodes, guaranteeing a temporal resolution from 5 kS/s to 20 kS/s for each electrode. A 128 × 190 MEA system was fabricated in a 110-nm CMOS process, and each readout channel consumes 81 μW at 1.5-V supply voltage featuring input-referred noise of 1.48 μVrms without multiplexing and 5.4 μVrms with multiplexing at the action-potential band (300 Hz-10 kHz).

A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications

To increase the light detection and ranging (LiDAR) system spatial resolution, the multiple photodetectors are typically deployed in the receiver. An equivalent linear-array receiver with multiplexing operation scheme is presented for the direct time of flight (dToF) LiDAR applications. In particular, the analog front-end (AFE) circuit of the proposed receiver mainly consists of eight transimpedance preamplifiers (preTIAs), a dummy preTIA, a post amplifier (PA) with an 8-to-1 multiplexer, an analog output buffer and a timing discriminator. The proposed AFE circuit, which achieves a transimpedance gain of ~106 dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> , a bandwidth of ~220 MHz, an equivalent input-referred noise current of ~5.1 pA/Hz0.5 and a channel switchover time of 6 ns, was fabricated in a 65 nm standard CMOS technology. The associated DC power consumption is 137 mW with a power supply of 2.5 V. The total area of the proposed AFE circuit, which includes the circuit core, bias circuits and I/O PADs, is approximately equal to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.2\times 1.2$ </tex-math></inline-formula> mm2.

0.6-V 1.65-μW Second-Order Gm-C Bandpass Filter for Multi-Frequency Bioimpedance Analysis Based on a Bootstrapped Bulk-Driven Voltage Buffer

A bootstrapping technique used to increase the intrinsic voltage gain of a bulk-driven MOS transistor is described in this paper. The proposed circuit incorporates a capacitor and a cutoff transistor to be connected to the gate terminal of a bulk-driven MOS device, thus achieving a quasi-floating-gate structure. As a result, the contribution of the gate transconductance is cancelled out and the voltage gain of the device is correspondingly increased. The technique allows for implementing a voltage follower with a voltage gain much closer to unity as compared to the conventional bulk-driven case. This voltage buffer, along with a pseudo-resistor, is used to design a linearized transconductor. The proposed transconductance cell includes an economic continuous tuning mechanism that permits programming the effective transconductance in a range sufficiently wide to counteract the typical variations that process parameters suffer during fabrication. The transconductor has been used to implement a second-order Gm-C bandpass filter with a relatively high selectivity factor, suited for multi-frequency bioimpedance analysis in a very low-voltage environment. All the circuits have been designed in 180 nm CMOS technology to operate with a 0.6-V single-supply voltage. Simulated results show that the proposed technique allows for increasing the linearity and reducing the input-referred noise of the bootstrapped bulk-driven MOS transistor, which results in an improvement of the overall performance of the transconductor. The center frequency of the bandpass filter designed can be programmed in the frequency range from 6.5 kHz to 37.5 kHz with a power consumption ranging between 1.34 μW and 2.19 μW. The circuit presents an in-band integrated noise of 190.5 μVrms and is able to process signals of 110 mVpp with a THD below −40 dB, thus leading to a dynamic range of 47.4 dB.

Low-Noise Potentiostat Readout Circuit with a Chopper Fully Differential Difference Amplifier for Glucose Monitoring

This paper presents a low-noise potentiostat readout circuit with a chopper fully differential difference amplifier (FDDA) for glucose monitoring. Glucose monitoring is necessary for the early diagnosis of diabetes complications and for health management. Ammeter electrochemical sensors are widely used for glucose detection, and in general, a three-electrode structure of a reference electrode (RE), a counter electrode (CE), and a working electrode (WE) is implemented with a potentiostat structure. A low-noise characteristic of the readout circuit is essential for highly accurate glucose monitoring. The chopping technique can reduce low-frequency noises such as 1/f noise and can achieve the required low-noise characteristic. The proposed potentiostat readout circuit is based on a low-noise chopper FDDA with a class-AB output stage. The implementation of the chopper FDDA scheme of the potentiostat readout circuit can decrease the number of amplifiers in the control part of the potentiostat, with reduced power consumption and a wide dynamic output range. The negative feedback loop of the inverting amplifier scheme with the FDDA maintains the voltage between the WE and RE constants. The negative feedback loop tracks the reference voltage of the RE with an input voltage of the WE. The proposed potentiostat readout circuit is designed in the standard 0.18 µm CMOS process, and the simulated current consumption is 48.54 μA with a 1.8 V power supply. The simulated input-referred noise level was 8.53 pArms.

Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier

This article presents a delta–sigma modulator (DSM) using a cascoded floating-inverter-based dynamic amplifier. The proposed cascoded dynamic amplifier achieves more than 50-dB dc gain while maintaining an HD3 of better than –110 dBc for signal swings less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$300~\mathrm {mV_{ppd}}$ </tex-math></inline-formula> . Compared to the previously reported two-stage floating inverter amplifier (FIA), the cascoded FIA has a lower and a process invariant input-referred noise, making it an ideal choice for high-resolution ADCs. We also show that, when such a single-stage dynamic amplifier, which has a time-varying transconductance, is used in closed-loop switched-capacitor circuits, the settling bandwidth depends on the average transconductance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m,\rm avg}$ </tex-math></inline-formula> during the settling interval. A detailed analysis reveals that, when the floating inverter structure operates in weak inversion for most of the time (which is the power-efficient way to bias the amplifier), this average transconductance depends strongly on the reservoir capacitance value and only weakly on the transistor dimensions. Besides, it is less sensitive to temperature variations, unlike the transconductance of a conventional OTA biased in weak inversion. We also quantitatively derive and show that the cascoded FIA is more power-efficient than a conventional static-current biased operational transconductance amplifier. Using the cascoded FIA, a discrete-time DSM has been designed and fabricated in a 180-nm CMOS process. The modulator runs at 3.072 MHz while consuming 189 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> from a 1.8-V supply. In a bandwidth of 24 kHz, the measured SNR/SNDR/SFDR is 96.4/96.2/114 dB, respectively.

0.342 nW Class-AB enhanced flipped source follower low pass filter for biomedical applications.

Owing to the impact of process voltage and temperature variations, the design of low-power low-pass filters (LPFs) with improved linearity is still one of the most challenging tasks for effective biological signal processing. This paper presents the design of a fourth-order Class-AB enhanced flipped source follower (EFSF) LPF circuit aimed at the detection of electroencephalography signals. The simulated results attained using complementary metal-oxide-semiconductor 180nm technology node in Cadence Analog Design Environment demonstrate that the EFSF LPF emulates a DC-gain of -88 mdB with a bandwidth of 100Hz and consumes 0.342 nW power from a supply voltage of 0.5V. The calculated figure of merit for the proposed filter is 5.983 × 10-15J with a dynamic range (DR) of 43.54 dB and input-referred noise of 91 µVrms. It consumes an area of 0.0458mm2. To check the robustness of the proposed filter circuit, we performed Monte Carlo simulations with 200 runs. The statistical results achieved for the DC-gain, DR, and total harmonic distortion of the proposed filter show mean values of -188.09 mdB, 43.10 dB, and -41.85 dB along with standard deviation values of 285.21 mdB, 718.72 mdB, and 4.52 dB, respectively. The proposed Class-AB EFSF LPF can be used to achieve high power efficiency in future low-voltage and low-power biological systems.

A 0.00426 mm2 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording

Driven by needs in neuroscientific research, future neural interface technologies demand integrated circuits that can record a large number of channels of neural signals in parallel while maintaining a miniaturized physical form factor. Using conventional methods, it is challenging to reduce circuit area while maintaining the high dynamic range, low noise, and low power consumption required in the neural application. This paper proposes to address this challenge using a VCO-based continuous-time delta-sigma modulator (CTDSM) circuit, which can record and digitize neural signals directly without the need for front-end instrumentation amplifiers and anti-aliasing filters, which are limited by the abovementioned circuit-area performance tradeoff. Thanks to the multi-level quantization and intrinsic mismatch-shaping capabilities of the VCO-based approach, the proposed first-order CTDSM can achieve comparable electrical performance to a higher-order CTDSM while offering further area and power reductions. We prototyped the circuit in a 22-channel test chip and demonstrate, based on the chip measurement results, that the proposed modulator occupies an area of 0.00426 mm2 while achieving input-referred noise levels of 6.26 and 3.54 µVrms in the action potential (AP) and local field potential (LFP) bands, respectively. With a 77.6 dB wide-dynamic range, the noise and total harmonic distortion meet the requirements of a neural interface with up to 149 mVpp input AC amplitude or up to ±68 mV DC offsets. We also validated the feasibility of the circuit for multi-channel recording applications by examining the impact of cross-channel VCO oscillation interferences on the circuit noise performance. The experimental results demonstrate the proposed architecture is an excellent candidate to implement future multi-channel neural-recording interfaces.

A 2.71‐pA/√Hz ultra‐low noise, 70‐dB dynamic range CMOS transimpedance amplifier with incorporated microstrip line techniques over extended bandwidth

AbstractRecent advancements in the area of telemedicine have focused on remote patient monitoring services as a new frontier in medical applications. The present work reports a 65‐nm complementary metal–oxide–semiconductor (CMOS)‐based transimpedance amplifier (TIA) in an optical radar system for non‐contact patient monitoring. A T‐shaped microstrip line (MSL) integrated with variable gain common source TIA using MSL peaking technique and off‐chip post‐amplification integration is a newly proposed architecture to achieve a ultra‐low noise, high dynamic range (DR) and high figure of merit over broadband than a traditional TIAs. First, the integrated T‐shaped MSL develops an additional resonant frequency that resonates with a photodiode capacitance improving the bandwidth performance at higher Q values. Second, the shunt MSL peaking technique that introduces an additional conjugate pole‐pair that cancels the effect of input capacitance helps to further improve the bandwidth of the TIA. Finally, an active feedback concept achieves a wide linear dynamic range enabling high TIA detectability. The proposed TIA realizes an impedance bandwidth of 770 MHz ranging from 7.12 to 7.89 GHz with a transimpedance gain of 105.1 dBΩ and ultra‐low input‐referred noise (IRN) density of 2.71 pA/√Hz. A high linear DR of 70 dB is achieved by employing a variable gain control scheme with a low group delay variation of 0.81 ns. The proposed work demonstrates a 1‐Gb/s data rate while a bit‐error rate less than 10−12 is achieved. The TIA consumes a power of 0.82 mW under the supply voltage of 1.2 V.

A fully dynamic third-order EF-CIFF noise-shaping SAR ADC with NTF zeros optimization and passive integration

In this paper, a third-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) is proposed which is simple and fully dynamic. A passive integrator is utilized in the feed-forward (FF) path of a second-order NS-SAR ADC with 2nd-order error-feedback (EF) filter to reduce the effect of inband quantization and comparator noise. The integrator implements a passive gain of 4x to make up its loss arising from the charge sharing between the integrator and digital-to-analog converter capacitors at the integration phase. Another advantage of the proposed structure is employing a simple low noise and low power one-input pair comparator unlike many published NS-SAR ADCs which use a comparator with multi-input pairs leading to enhanced comparator input-referred noise and power consumption. In this work, the zeros of the noise transfer function are optimized to enhance inband noise suppression. The proposed ADC is designed at circuit level using 0.18 μm TSMC CMOS technology with Cadence Virtuoso tool. The oversampling ratio, sampling frequency, and bandwidth are 8, 2.5 MS/s, and 156.25 kHz, respectively. According to the detailed post-layout simulation results, the achieved signal-to-noise and distortion ratio of the simulated ADC is 83.1 dB with 70.3 µW power consumption from a 1.1 V supply.

On Noise Modeling of Capacitive Feedback Transimpedance Amplifiers in CMOS

The work reports on the development of a detailed noise current model for a low-noise capacitive feedback transimpedance amplifier (TIA) in CMOS. The proposed TIA circuit implements the programmable-gain using an array of discretely controlled feedback capacitors and resistances in the biasing circuit and is originally designed bearing in mind low-noise requirements for optical time-domain reflectometer (OTDR) applications with the base gain of 10 kΩ at 1 GHz bandwidth and noise levels below 5.0 pA/Hz. The newly developed model for input-referred noise current spectral density complements the previously suggested transimpedance gain model and takes into account both the primary and secondary noise sources so far ignored in the models known in the literature. The proposed noise model consists of five terms and includes the effects caused by biasing components of the input stage and the noise shaping from the source follower. The performance of the developed noise model is evaluated using the post-layout simulation in 0.18 μm CMOS and 0.25 μm BiCMOS technologies, and a close match of the proposed model is demonstrated in the results of the post-layout simulation with the noise level below 1.8 pA/Hz for the base gain configuration in CMOS. A comparison to available noise models from the literature confirms that previously known noise models for this promising TIA architecture omitted important noise components present in practical and physically realizable circuits and, therefore, resulted in underestimating the base noise level by a factor of two to three, while completely ignoring the flicker noise mapping in the low-frequency range.

A Low Power ROIC with Extended Counting ADC Based on Circuit Noise Analysis for Sensor Arrays in IoT System

As the Internet of Things (IoT) is rapidly integrated into our daily life, the demand for high performance readout integrated circuit (ROIC) design for sensor arrays is boosting. This paper presents a low power, low noise ROIC with 14-bit column-parallel extended counting (EC) ADCs for sensor arrays targeting the IoT applications. The proposed EC-ADC adopts a pseudodifferential architecture to cancel even-order nonlinearity. The analog front-end is a G m stage, which employs a current-reuse topology to boost the transconductance and reduce noise without increasing current consumption. The upper 9-bit conversion is implemented during integration, and the residual voltage is converted by a 5-bit single-slope (SS) ADC, where the comparator is reused. A ping-pong integrator is proposed to reduce the reset time and improve linearity, eliminating the power-hungry CTIA structure. The ROIC is designed in 0.18 μm 1P5M CMOS process for a 640 × 480 sensor array. Power consumption of the ROIC is 33 mW, and each column ADC consumes 40.1 μW. Simulation results show an input-referred noise of 0.89 LSB (1.74 μVrms), an integral nonlinearity of +0.92/-0.70 LSB, an ENOB of 12.87 bits, and a FoM of 131.1 fJ/step.

A VCO-Based CTDSM With Integrated Phase Error Correction for Neural Interface

Neural recording front-ends with voltage controlled-oscillator (VCO) based continuous-time <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\rm \Delta \Sigma $ </tex-math></inline-formula> modulators (CTDSM) enable direct analogue to digital conversion with minimized aliasing and hardware overhead, however, their performance suffers from phase glitches due to sampling meta-stability and large interference from input or power line. This brief presents a self-correction scheme for multi-phase VCO-based CTDSM. The VCO’s phase pattern is processed in both continuous-time (CT) and discrete-time (DT) domain with real-time error detection and correction to guarantee robust operation. Based on the this scheme, a phase counter can be implemented to assist the XOR-based phase detector (PD) with minimized error, extending the phase detection range, therefore leading to improved quantization resolution and system linearity even with glitches. Fabricated in a 180-nm CMOS process, the prototype achieves 70.7 dB SNDR, 71.0 dB SNR, 83.1 dB SFDR and 71.2 dB DR within 10 kHz bandwidth. The measured input referred noise (IRN) is 5.94 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{V}\rm _{rms}$ </tex-math></inline-formula> over 0.5 Hz-10 kHz bandwidth. The performance of this self-correction scheme is verified by injecting phase error with different frequency. A maximum of 16.2 dB improvement of SNDR can be observed for 625 Hz injected interference.

Design and Simulation of Low Power Differential Transimpedance Amplifier Using Degenerations Capacitors

In today’s internet-connected culture, high-speed data transmission techniques are in high demand. Optical communication is most used techniques for data transmission with speed. High-speed amplifiers are needed, nevertheless, to obtain high gains and transform current signals into voltage gains. This is accomplished via transimpedance amplifiers, a crucial component of optical receivers. In this work, a high-speed transimpedance amplifier with negative degeneration capacitors and complete differential operation is built. The proposed design has a transimpedance gain of approximately 52.4 dB at 19.8 GHz and an average input-referred noise current of roughly 23.3 pA/√Hz. The suggested circuit also has an high gain, and low input-referred noise, excellent bandwidth all of which contribute to its low power consumption of roughly 215 uW. This makes it appropriate for Internet of Things (IoT) devices, smart devices, mobile phones, laptops, and other computer peripherals.

A 10 M Ω, 50 kHz-40 MHz Impedance Measurement Architecture for Source-Differential Flow Cytometry.

A low-power, impedance-based integrated circuit (IC) readout architecture is presented for cell analysis and cytometry applications. A three-electrode layout and source-differential excitation cancels baseline current prior to the sensor front-end, which enables the use of a high-gain readout circuit for the difference current. A lock-in architecture is employed with down-conversion and up-conversion in the feedback loop, enabling high closed-loop gain (up to 10 M Ω) and high bandwidth (up to 40 MHz). A hybrid-RC feedback network mitigates the SNR degradation seen over a wide operating frequency range when using purely capacitive feedback. The effect of phase shift on the closed-loop system gain and noise performance are analyzed in detail, along with optimization strategies, and the design includes fine-grained phase adjustment to minimize phase error. The impedance sensor was fabricated in a 0.18 μ m CMOS process and consumes 9.7 mW with an operating frequency from 50 kHz to 40 MHz and provides adjustable bandwidth. Measurements demonstrate that the impedance sensor achieves 6 pA [Formula: see text] input-referred noise over 200 Hz bandwidth at 0.5 MHz modulation frequency. Combined with a microfluidic flow cell, measured results using this source-differential measurement approach are presented using both monodisperse and polydisperse sample solutions and demonstrate single-cell resolution, detecting 3 μ m diameter particles in solution with 22 dB SNR.

A CMOS AFE With 37-nA rms Input-Referred Noise and Marked 96-dB Timing DR for Pulsed LiDAR

This paper presents an analog front-end (AFE) circuit with marked timing point for pulsed time-of-flight LiDAR that employs either sampling- or event-based timing approach. The proposed AFE adopts a dual-mode structure for its pre-amplifier which can be configured as a charge-sensitive amplifier (CSA) or a gated active load-assisted TIA (GALA-TIA), depending on the intensity of input current. As a result, both the sensitivity and dynamic range (DR) of the AFE have been effectively improved. In addition, the zero-crossing point of the output signal has been marked as the timing point with a built-in pulse shaper, which allows the back-end circuits of LiDAR receiver discriminate the timing conveniently and accurately. The measured input-referred RMS noise current of the proposed AFE is 37 nA. With dual-mode control, a linear output DR of 80 dB and a wide timing DR of 96 dB with walk error no more than ±160 ps have been achieved. For single-shot measurement application, only CSA mode was enabled and the pulse widths of saturated output signals have been measured to compensate the walk errors, which realized a timing DR of 78 dB with accuracy of ±150 ps. The averaged power consumption is 66 mW and the total silicon area is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.79\times 0.42\,\,mm^{2}$ </tex-math></inline-formula> in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process.

A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction.

This paper presents a low noise 0.6-V 400-kS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for input-referred noise reduction. A dual-domain comparator is proposed to optimize the power, noise, and sampling rate of the ADC in the 10-bit conversion. In order to optimize the figure of merits (FoM) of the ADC, the 10-bit conversion consists of a 7-bit coarse conversion with the double-tail dynamic comparator and a 3-bit fine conversion with the VCDL-based time-domain comparator. An asynchronous timing controller is also proposed to improve the ADC sampling rate and optimize the power consumption of the dual-domain comparator. The proposed SAR ADC is fabricated in 180-nm CMOS technology with an area of 0.836 mm2. At a 0.6-V supply voltage and a 400-kS/s sampling rate, the implemented SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 56.59 dB and an effective number of bits (ENOB) of 9.16 bits. The peak values of DNL and INL are +0.47/−0.53 LSB and +0.92/−0.64 LSB, respectively. The FoM is 10.31 fJ/conversion step with a power consumption of 2.36 μW.

High Gain, Low Noise and Power Transimpedance Amplifier Based on Second Generation Voltage Conveyor in 65 nm CMOS Technology.

A transimpedance amplifier (TIA) based on a voltage conveyor structure designed for high gain, low noise, low distortion, and low power consumption is presented in this work. Following a second-generation voltage conveyor topology, the current and voltage blocks are a regulated cascode amplifier and a down converter buffer, respectively. The proposed voltage buffer is designed for low distortion and low power consumption, whereas the regulated cascode is designed for low noise and high gain. The resulting TIA was fabricated in 65 nm CMOS technology for logic and mixed-mode designs, using low-threshold voltage transistors and a supply voltage of ±1.2 V. It exhibited a 52 dBΩ transimpedance gain and a 1.1 GHz bandwidth, consuming 55.3 mW using a ±1.2 V supply. Our preamplifier stage, based on a regulated cascode, was designed considering detector capacitance, bonding wire, and packaging capacitance. The voltage buffer was designed for low-power consumption and low distortion. The measured input-referred noise of the TIA was 22 pA/√Hz. The obtained total harmonic distortion of the TIA was close to 5%. In addition, the group delay is constant for the considered bandwidth. Comparisons against published results in terms of area (A), power consumption (P), bandwidth (BW), transimpedance gain (G), and noise (N) are were performed. Both figures of merit FoMs—the ratio √ (G × BW) and P × A—and FoM/N values demostrated the advantages of the proposed approach.

Analysis and Design of Inductorless Transimpedance Amplifier Employing Nested Feedforward Noise-Canceling Amplifiers

In this article, we propose a nested feedforward noise canceling (NFF-NC) technique for transimpedance amplifier (TIA) in optical link communication. The proposed technique minimizes the noise voltages due to both the first and second stages of the TIA, which provides substantial improvement in its noise performance over conventional noise canceling (NC) topology. Comprehensive analysis and comparison are performed between two techniques. While not degrading other key performance parameters (e.g., bandwidth, gain, and power consumption), our proposed scheme presents 30% noise reduction compared to conventional scheme. The proposed NC architecture provides the improved stability since NFF-NC scheme inherently presents an additional left half-plane (LHP) zero due to the FF-stage. The loop stability performance is verified over several process corners, temperatures, and voltage variations confirming the detailed analysis in its loop gain and loop parameters. The proposed NFF-NC TIA was implemented in a 65-nm CMOS technology. The implemented TIA consumes 10.1 mW of power from a 1.3-V supply and occupies 0.037 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of core area. The measurement results show that the proposed TIA presents dc transimpedance gain of 56.3 dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> and bandwidth (−3 dB) of 6.5 GHz. An average input-referred noise current density, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\overline {i_{n,\text {in},\text {avg}}}$ </tex-math></inline-formula> , is 15.1 pA/(Hz) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1/2</sup> over the bandwidth. Eye diagram is also measured with a pseudorandom binary sequence (PRBS) of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> – 1 with the data rate at 8.5 Gb/s.

A 26.5 pArms Neurotransmitter Front-End With Class-AB Background Subtraction.

This paper presents an analog front-end (AFE) for fast-scan cyclic voltammetry (FSCV) with analog background subtraction using a pseudo-differential sensing scheme to cancel the large non-faradaic current before seeing the front-end. As a result, the AFE can be compact and low-power compared to conventional FSCV AFEs with dedicated digital back-ends to digitize and subtract the background from subsequent recordings. The reported AFE, fabricated in a 0.18- μ m CMOS process, consists of a class-AB common-mode rejection circuit, a low-input-impedance current conveyor, and a 1st-order current-mode delta-sigma (ΔΣ) modulator with an infinite impulse response quantizer. This AFE achieves an effective dynamic range of 83 dB with a state-of-the-art 39.2 pArms input-referred noise when loaded with a 1 nF input capacitance (26.5 pArms open-circuit) across a 5 kHz bandwidth while consuming an average power of 3.7 μW. This design was tested with carbon-fiber microelectrodes scanned at 300 V/s using flow-injection of dopamine, a key neurotransmitter.

A [formula omitted]110 dB THD rail-to-rail class-AB programmable gain amplifier with common-mode-detection-based transconductance linearization scheme

A low total harmonic distortion (THD) programmable gain amplifier (PGA) with dual operational amplifiers (op-amps) for electrocardiogram (ECG) signal acquisition applications is presented. The proposed op-amp comprises the rail-to-rail input stage and class-AB output stage. To solve the transconductance (gm) variation caused by the supply voltage changes in rail-to-rail amplifiers with the traditional DC level-shifting technique, a common-mode-detection-based transconductance linearization scheme is proposed in this paper, associated with a 7-steps resistor-feedback digital gain control from 1 V/V to 12 V/V, which can realize less than 2.7% transconductance variations. The proposed rail-to-rail class-AB PGA is implemented in 0.18-μm CMOS technology with 2.7-V∼5-V power supply voltage and 0.07-mm2 core area. Spice simulation results show that the THD is −110 dB with an input signal of 5 mVpp and the input-referred noise spectrum density is 0.5 μV/Hz at a 10-Hz frequency point, after adopting an 8-kHz chopping. The total power consumption including the bias circuit is 81 μW at 2.7 V.