Input-referred Noise Research Articles

A 10-Gb/s Inductorless Low-Power TIA With a 400-fF Low-Speed Avalanche Photodiode Realized in CMOS Process

Compared with SiGe technology, the limits of low transition frequency and low transconductance per unit current of CMOS technology result in poor noise, narrow bandwidth, and high power consumption in high-speed transimpedance amplifiers. The aforementioned issues are further exacerbated while using a low-speed low-cost photodiode. In this study, an equalization technique is proposed to increase the feedback resistance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {R_{F}}$ </tex-math></inline-formula> , achieving low noise and bandwidth extension of the chip. A novel inductorless bandwidth extension technique is proposed to increase the bandwidth of high-speed channel by 37.5%. In addition, a new current reuse technique is proposed to inject the output stage’s tail current into the input stage to achieve a high gain, saving power consumption by 20%. We achieve 10-Gb/s operation with a 400-fF avalanche photodiode (APD) using 65-nm CMOS technology. The bandwidth is 6.8 GHz, the transimpedance gain is 66 dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol{\Omega }$ </tex-math></inline-formula> , the average input-referred noise current is 11.9 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\surd $ </tex-math></inline-formula> Hz, and the average sensitivity is −22.4 dBm at a BER of 1e−12. The SF-TIA chip takes up 0.56 mm2 and consumes 26 mA from a 3.3-V supply.

An AC-Coupled 1st-order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition.

The current demand for high-channel-count neural-recording interfaces calls for more area- and power-efficient readout architectures that do not compromise other electrical performances. In this paper, we present a miniature 128-channel neural recording integrated circuit (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs), which can achieve a very good compromise between area, power, noise, input range and electrode DC offset cancellation. An AC-coupled 1st-order digitally-intensive architecture is proposed to achieve this compromise and to leverage the advantages of a highly-scaled technology node. A prototype NRIC, including 128 channels, a newly-proposed area-efficient bulk-regulated voltage reference, biasing circuits and a digital control, has been fabricated in 22-nm FDSOI CMOS and fully characterized. Our proposed architecture achieves a total area per channel of 0.005 mm2, a total power per channel of 12.57 , and an input-referred noise of 7.7 ± 0.4 in the AP band and 11.9 ± 1.1 in the LFP band. A very good channel-to-channel uniformity is demonstrated by our measurements. The chip has been validated in vivo, demonstrating its capability to successfully record full-band neural signals.

Design of a Low-Power Ground-Free Analog Front End for ECG Acquisition.

This article presents the design of a low-power ground-free (two-electrode) analog front end (AFE) for ECG acquisition. At the heart of the design is the low-power common-mode interference (CMI) suppression circuit (CMI-SC) to help minimize the common-mode input swing and prevent turning on the ESD diodes at the input of the AFE. Fabricated in a 0.18- μm CMOS process with an active area of 0.8 [Formula: see text], the two-electrode AFE can tolerate CMI of up to 12 [Formula: see text], while consuming only 6.55 μW of power from a 1.2-V supply and exhibiting 1.67 μVrms of input-referred noise in a 1-100 Hz bandwidth. Compared to existing works, the proposed two-electrode AFE thus provides a 3× reduction in power for comparable noise and CMI suppression performances.

Design of a Current Sensing System with TIA Gain of 160 dBΩ and Input-Referred Noise of 1.8 pArms for Biosensor.

This paper proposes a high-gain low-noise current signal detection system for biosensors. When the biomaterial is attached to the biosensor, the current flowing through the bias voltage is changed so that the biomaterial can be sensed. A resistive feedback transimpedance amplifier (TIA) is used for the biosensor requiring a bias voltage. Current changes in the biosensor can be checked by plotting the current value of the biosensor in real time on the self-made graphical user interface (GUI). Even if the bias voltage changes, the input voltage of the analog to digital converter (ADC) does not change, so it is designed to plot the current of the biosensor accurately and stably. In particular, for multi-biosensors with an array structure, a method of automatically calibrating the current between biosensors by controlling the gate bias voltage of the biosensors is proposed. Input-referred noise is reduced using a high-gain TIA and chopper technique. The proposed circuit achieves 1.8 pArms input-referred noise with a gain of 160 dBΩ and is implemented in a TSMC 130 nm CMOS process. The chip area is 2.3 mm2, and the power consumption of the current sensing system is 12 mW.

An expandable 36‐channel neural recording ASIC with modular digital pixel design technique

AbstractThis paper presents the design and implementation of an expandable neural recording ASIC for multiple‐channel neural recording applications. The ASIC consists of 36 modular digital pixels (MDPs) and a global digital controller (GDC) circuit. Each MDP has an analog frontend (AFE) circuit, a 12‐bit successive approximation register ADC (SAR ADC), and a local digital controller (LDC) circuit. It achieves 5.9‐μV input referred noise (IRN), 10.8‐effective number of bits (ENOB), 37.8‐μW power consumption, and 0.095 mm2 area per channel. The ASIC is implemented in commercial SMIC 0.18‐μm CMOS process and validated by in‐vivo experiment on a lab mouse with a 36‐channel silicon‐based neural probe.

A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes

A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude modulation (4-PAM) with −8.2-dBm sensitivity is presented in support for optical receivers required in the next-generation intra-data center links. A proposed three-stage TIA is comprised of a shunt-feedback stage followed by digitally programmable continuous-time linear equalizers (CTLEs) and a variable gain amplifier (VGA). Broadband low-noise design is achieved by having the first stage with much lower bandwidth (BW) followed by the proposed BW recovering CTLEs. A low-power design is supported by the inverter-based single-ended architecture with a single-ended-to-pseudo-differential conversion in the last stage. TIA’s BW extension is further supported by optimizing the photodiode-to-receiver (PD-to-RX) interconnect and utilizing several inductive peaking techniques. It achieves 63-dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> gain, 32-GHz BW, and an average input-referred current noise density of 16.9 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sqrt {\text {Hz}}$ </tex-math></inline-formula> while operating at 0.9-V supply and consuming 47-mW power. Opto-electrical measurements are performed on a co-packaged prototype comprised of identical proposed TIAs in CMOS with combinations of various commercial PDs and PD-to-RX interconnect lengths confirming 112-Gb/s 4-PAM reception meeting pre-forward error correction (FEC) symbol error rate (SER) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.8 \times 10 ^{-4}$ </tex-math></inline-formula> without any post-equalization.

Analysis and Design of VCO-Based Neural Front-End With Mixed Domain Level-Crossing for Fast Artifact Recovery

Concurrent neural signal instrumentation withstanding neural stimulation artifacts is essential for bi-directional neural interfaces to guarantee signal integrity. In this work, different front-end structures and stimulation artifact mitigation techniques are firstly reviewed to benchmark their step response speed. Then, a mixed domain level-crossing scheme is proposed to achieve fast dynamic response with minimized hardware overhead. The benefit of extending the phase detection range of the phase detectors in VCO-based continuous time <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\rm \Delta \Sigma $ </tex-math></inline-formula> modulators is investigated with stability and noise consideration. Then a shift-register-based phase counter is proposed to extend the phase detectors’s detection range, thereby increase quantization resolution and stability margin for in-band noise optimization. The proposed VCO-based neural front-end was fabricated in a 180 nm CMOS process. The prototype achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.38~\mu $ </tex-math></inline-formula> Vrms input-referred noise over 0.5 Hz-10 kHz bandwidth. With a linear input range of 120 mVpp, it exhibits a SNDR of 71.6 dB and a DR of 77.0 dB, which could be further extended up to 100 dB in the artifact adaption mode. Measurements verify that the proposed neural front-end can recover from rail-to-rail differential mode or common mode artifacts within 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> (minimum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.25~\mu \text{s}$ </tex-math></inline-formula> ) while the superposed small signal can be recorded uninterruptedly.

Novel tunable current feedback instrumentation amplifier based on BBFC OP-AMP for biomedical applications with low power and high CMRR

The paper presents a novel low power, low noise and high CMRR current feedback instrumentation amplifier (CFIA) design for biomedical signal acquisition i.e. EEG/ECG applications is presented. The proposed instrumentation amplifier performance is evaluated using 0.18μm, CMOS technology with 1.8 V supply and results are obtained in Cadence EDA tool. The proposed CFIA is implemented using a dual output bandwidth boosted folded cascode operational amplifier (BBFC OP-AMP) active block. In this paper the proposed CFIA performance parameters has been considered for optimization to get better results by using the idea of signal to noise ratio (SNR) with Taguchi design of experiments (Taguchi DoE) and analysis of variance (ANOVA) to estimate the most important independent variable which control the performance of the design. The bias voltage, channel length and width of input MOS transistors have been selected to optimize the proposed circuit performance. The proposed CFIA structure have 50.33 to 69.67 dB tunable differential gain, common mode rejection ratio (CMRR) of 143.19 dB, tunable bandwidth of 148.24 kHz to 1.31 MHz, dynamic range (DR) of 74.31 dB and 297.73 dB of figure of merit (FoM). The CFIA shows an equivalent input referred noise (IRN) of 0.586 μV at 0.1 Hz to 148.24 kHz frequency range, with total power dissipation of 102.73 μW and occupies 8194μm2 of core area. The simulation results of the proposed CFIA are close to the predicted solution obtained from ANOVA. The PVT analysis and post layout simulation has been performed to check the robustness of the proposed design. The proposed design has been compared with the other existing literature which shows the competence of the design.

A Wireless Headstage System Based on Neural-Recording Chip Featuring 315 nW Kickback-Reduction SAR ADC.

Wireless neural-recording instruments eliminate the bulky cables in multi-channel signal transmission, while the system size should be reduced to mitigate the impact on freely-moving animals. As the battery usually dominates the system size, the neural-recording chip should be low power to minimize the battery in long-termly monitoring. In general, a neural-recording chip consists of an analog front end (AFE) and an 8 bit -10 bit analog-to-digital converter (ADC), while it's challenging to design an ADC with an 8 -10 effective number of bits (ENOB) and sub- μ W power consumption due to the kickback noise. In this work, we propose a kickback-reduction technique for a successive-approximation-register (SAR) ADC based on neural-recording chip. Fabricated in 65 nm CMOS process, the proposed technique reduce the ADC power to 315 nW, resulting in an 8-channel neural-recording chip with 249 μW in total. Measured results show that the chip achieves an ADC ENOB of 9.73 bits, as well as an AFE gain of 43.3 dB and input-referred noise (IRN) of 9.68 μVrms in a bandwidth of 0.9 Hz -7.2 kHz. Combined with a BLE chip and a PCB antenna, the chip is implemented into a 2.6 g wireless headstage system (w/o battery), and an in-vivo demonstration is conducted on a male Sprague-Dawley rat with Parkinson's disease. The headstage system transfers the in-vivo neural signals to a commodity smartphone through BLE, and the miniature size induces little impact on freely-moving activities.

A 43.3-μW Biopotential Amplifier With Tolerance to Common-Mode Interference of 18 Vpp and T-CMRR of 105 dB in 180-nm CMOS

In this article, we present an electrocardiogram (ECG) amplifier that has a large total CMRR (TCMRR) regardless of contact impedance mismatch and a large tolerance to common-mode interference (CMI). To achieve these features, an adaptive TCMRR enhancing loop is implemented in parallel with a charge-pump-based common-mode suppressing loop (CMSL). It adjusts the CMI current through each contact impedance so that common-mode (CM) to differential-mode (DM) conversion is minimized. We also propose a fast settling technique for the adaptive loop so that contact impedance variation can be tracked fast enough to allow robust ECG acquisition. A prototype chip fabricated in 180-nm CMOS achieves TCMRR larger than 105 dB even when there is contact impedance mismatch of up to 30%. It also achieves tolerance to CMI of 18 VPP at 60 Hz and input-referred noise of 1.90 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\rm V_{rms}$ </tex-math></inline-formula> while consuming 43.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> .

IEMS: An IoT-Empowered Wearable Multimodal Monitoring System in Neurocritical Care

IoT-empowered wearable multimodal monitoring system (IEMS), an IEMS for neurocritical care is developed to perform simultaneous monitoring of 8-channel electroencephalogram (EEG), 2-channel regional cerebral oxygen saturation (rSO2) based on near-infrared spectrum (NIRS), body surface temperature, electrocardiogram (ECG), photoplethysmography (PPG), and bioimpedance (Bio-Z). The IoT platform and wireless devices enable the patients’ signals available for remote diagnosis. Besides, analysis functions and artificial intelligence (AI) algorithms could be embedded in both the bedside platform and the cloud server to support physicians with clinical decisions. In the multimodal neural monitoring device, the following designs are adopted to face the neurological intensive care unit (NICU) application. Active electrodes and preamplifying free topology provide better signal quality and a larger dynamic range (DR). Dedicated low-power designs ensure the device lasts 10 h of operation. A nonwoven headset improves long-term wearability, which is also quick and easy to install. In the cardiovascular patch, the disposable electrode patch based on elastic materials ensures tight and comfortable contact with skin. Besides, the reusable wireless sensing module is tiny (20 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times16$ </tex-math></inline-formula> mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times9$ </tex-math></inline-formula> mm) but could measure ECG, PPG, and Bio-Z simultaneously. Electrical tests and human subject (healthy volunteers and NICU patients) studies were conducted to examine the performance. The EEG channels show 130.75-dB DR and 0.84- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu {}\text{V}_{\mathrm{ RMS}}$ </tex-math></inline-formula> input-referred noise, which also yields signals with high quality during human EEG monitoring. The NIRS channels exhibit good linearity and are able to operate under severe ambient interference. The temperature sensors show ±0.2 °C accuracy. Moreover, the system complies with mandatory standards for medical equipment. Overall, an IEMS can meet the requirements for NICU applications and could provide better comfort during long-term wearing.

A low-noise and mismatch-tolerant current-mirror-based potentiostat circuit for glucose monitoring

Potentiostat circuits are widely used to monitor biochemical signals such as glucose and viruses. Here, we proposed a potentiostat circuit that is an amperometric sensor with a three-electrode configuration. Low-noise and mismatch-tolerant characteristics are essential for the accurate measurement of biochemical signals. To achieve low-noise characteristics, we apply the chopper stabilization technique to a trans-impedance amplifier (TIA) and a control amplifier (CA). In addition, dynamic element matching (DEM) was adopted for the current mirror to achieve mismatch-tolerance. The proposed potentiostat consists of a CA, current mirror, and TIA. CA maintains the voltage between the working electrode (WE) and counter electrode (CE). The current mirror transmits a low-noise and mismatch-tolerant current signal to the TIA. The TIA converts the minute current signal into an amplified voltage signal. The proposed circuit was fabricated using a TSMC 180 nm CMOS process. The input-referred noise is 857 fA/√Hz at 1 Hz. The power consumption is 273.9 μW with a 1.8 V power supply.

A 29.5 dBm OOB IIP3 TIA Based on a Two-Stage Pseudo-Differential OTA With R-C Compensation and Cascode Negative Resistance

This paper presents a highly linear and wideband transimpedance amplifier (TIA) suitable for 5G Sub-6 GHz surface acoustic wave (SAW) filter-less receivers (RX). It is known that for the baseband TIA in a SAW-less RX, the high out-of-band (OOB) linearity is necessary to cope with huge OOB blockers. In other words, the input impedance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Z_in</i> ) of the TIAs should be as low as possible, which in turn necessitates high-gain, large-bandwidth (BW) operational transconductance amplifiers (OTA). In this work, a pseudo-differential two-stage OTA with 46 dB open-loop gain and 1 GHz unity-gain loop bandwidth (UGLB) is designed at low supply voltage (Vdd). To stabilize the differential mode (DM) loop, the phase margin (PM) is compensated with the zeros generated by the series of resistors and capacitors (R-C), and the gain margin is improved by the feed-forward technique. To stabilize the common mode (CM) loop without the degradation of the DM gain, a wideband common mode rejection (CMR) technique named cascode negative resistance (CNR) is proposed. This TIA prototype is implemented in a 40 nm low-power (LP) CMOS technology. The measured results show that the TIA achieves 56 MHz BW and 29.5 dBm OOB IIP3. The input impedance is below 29Ω in the concerned frequency range and the in-band (IB) input referred noise (IRN) is 120 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">uV_RMS</i> . The total chip power consumption is around 8.5 mW at 1.2 V supply voltage and the core area is as small as 0.015 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mm</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 672-nW, 670-nVrms ECG Acquisition AFE With Noise-Tolerant Heartbeat Detector

This paper presents an electrocardiogram acquisition analog front-end (AFE) with a noise tolerant heartbeat (HB) detector. Source degradation and transconductance bootstrap techniques are incorporated into the AFE to reduce the 1/f noise of the amplifier. Furthermore, the chopper modulation, DC-servo loop (DSL) and pre-charge technology are combined to reduce interference from the environment. A mixed-signal implementation of HB detector with the symmetric-comparison loop is proposed to reduce the power consumption and area, which also suppresses motion artifact interference by adaptive thresholds. Implemented in 0.18 μm CMOS process, the circuit only occupies an area of 0.122 mm2 and consumes 0.62 μW at a 1.2-V supply, of which AFE and HB detector consume 507 nW and 110 nW, respectively. Simulation results show that the gain and the CMRR of AFE range from 30-45 dB and 65-105 dB, respectively. The input-referred noise is 670 nVrms with a mid-band gain of 42 dB and a bandwidth ranging from 0.5 Hz to 1 kHz.

A Novel In-Home Sleep Monitoring System Based on Fully Integrated Multichannel Front-End Chip and Its Multilevel Analyses.

A novel in-home sleep monitoring system with an 8-channel biopotential acquisition front-end chip is presented and validated via multilevel data analyses and comparision with advanced polysomnography. The chip includes a cascaded low-noise programmable gain amplifier (PGA) and 24-bit [Formula: see text]-[Formula: see text] analog-to-digital converter (ADC). The PGA is based on three op-amp structure while the ADC adopts cascade of integrator feedforward and feedback (CIFF-B) architecture. An innovative chopper-modulated input-scaling-down technique enhances the dynamic range. The proposed system and commercial polysomnography were used for in-home sleep monitoring of 20 healthy participants. The consistency and significance of the two groups' data were analyzed. Fabricated in 180 nm BCD technology, the input-referred noise, input impedance, common-mode rejection ratio, and dynamic range of the acquisition front-end chip were [Formula: see text]Vpp, 1.25 GN), 113.9 dB, and 119.8 dB. The kappa coefficients between the sleep stage labels of the three scorers were 0.80, 0.76, and 0.79. The consistency of the slowing index, multiscale entropy, and percentile features between the two devices reached 0.958, 0.885, and 0.834. The macro sleep architecture characteristics of the two devices were not significantly different (all p [Formula: see text] 0.05). The proposed chip was applied to develop an in-home sleep monitoring system with significantly reduced size, power, and cost. Multilevel analyses demonstrated that this system collects stable and accurate in-home sleep data. The proposed system can be applied for long-term in-home sleep monitoring outside of laboratory environments and sleep disorders screening that with low cost.

Modeling and Simulation of Circuit-Level Nonidealities for an Analog Computing Design Approach With Application to EEG Feature Extraction

This article presents a design approach for the modeling and simulation of ultralow power (ULP) analog computing machine learning (ML) circuits for seizure detection using electroencephalography (EEG) signals in wearable health monitoring applications. In this article, we describe a new analog system modeling and simulation technique to associate power consumption, noise, linearity, and other critical performance parameters of analog circuits with the classification accuracy of a given ML network, which allows to realize a power and performance optimized analog ML hardware implementation based on diverse application-specific needs. We carried out circuit simulations to obtain nonidealities, which are then mathematically modeled for an accurate mapping. We have modeled noise, nonlinearity, resolution, and process variations such that the model can accurately obtain the classification accuracy of the analog computing-based seizure detection system. Noise has been modeled as an input-referred white noise that can be directly added at the input. Device process and temperature variations were modeled as random fluctuations in circuit parameters, such as gain and cut-off frequency. Nonlinearity was mathematically modeled as a power series. The combined system level model was then simulated for classification accuracy assessments. The design approach helps to optimize power and area during the development of tailored analog circuits for ML networks with the ability to potentially trade power and performance goals while still ensuring the required classification accuracy. The simulation technique also enables to determine target specifications for each circuit block in the analog computing hardware. This is achieved by developing the ML hardware model, and investigating the effect of circuit nonidealities on classification accuracy. Simulation of an analog computing EEG seizure detection block shows a classification accuracy of 91%. The proposed modeling approach will significantly reduce design time and complexity of large analog computing systems. Two feature extraction approaches are also compared for an analog computing architecture.

An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process

In this paper, a fully-differential transimpedance amplifier (TIA) providing a high gain-BW product (GBP) is introduced. In the proposed architecture, a cascode cross-coupled structure is employed to double the effective transconductance of the cascode devices, improving the BW of the TIA. Moreover, a differential architecture is implemented using an RC high-pass filter along with a buffer stage requiring smaller capacitance and resistance. Furthermore, a single-ended negative capacitance generation (NCG) circuit is employed at the input of the TIA to partially compensate for the input parasitic capacitances. A TIA including the proposed techniques, designed and laid out in a 16-nm FinFET process, demonstrates 57% and 79% better figure-of-merit compared to cascode and conventional TIAs designed along with the proposed TIA for a fair comparison, respectively. Post-layout simulations in companion with statistical analysis are employed to verify the effectiveness of the proposed architecture. From simulation results, the optical receiver achieves a peak transimpedance gain of 58.5 dBΩ, a BW of 14.8 GHz, an input-referred noise of 33.6 pA/Hz, and an eye-opening of 30 mV at a data-rate of 56 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole circuit consume 49 mW and occupies an active area of 0.0076 mm2.

Performance Analysis for Energy-Efficient Comparators

This work studies three different comparator proposed in recent years. Compared to the strnongARM latch as well as the Elzakker’s comparator, the dynamic comparator added cross-coupled devices that keeps the pre-amplifier’s integration nodes from fully discharge to the ground and thus improves energy performance. The dynamic bias latch-type comparator is an innovative design which added a tail capacitor to the pre-amplifier in order to block off the discharge route between the internal nodes and the ground. Though this design reduced the energy consumption significantly compared with the Elzakker’s comparator, it results in longer delay and only little improvement on the input-referred noise. The FIA dynamic comparator implemented a floating inverter amplifier (FIA) that utilizes a reservoir capacitor which cuts off its charging path and discharging path significantly reduced the energy consumption and improved noise performance to power itself.

Impact of the channel doping on the low-frequency noise of gate-all-around silicon vertical nanowire pMOSFETs

In this work, the impact of the channel doping density on the low-frequency noise of silicon Gate-All-Around (GAA) Vertical Nanowire (VNW) pMOSFETs on Silicon-on-Insulator (SOI) substrates will be described and discussed. It is demonstrated that the dominant fluctuation mechanism of the 1/f noise in the subthreshold regime changes from number (Δn) to mobility (Δμ) fluctuations with increasing p-type doping density of the silicon nanowires. At the same time, the lowest input-referred voltage noise Power Spectral Density is observed for an intermediate boron concentration in the nanowire of 5 × 1018 cm−3.

Low-Noise, Low-Power Readout IC for Two-Electrode ECG Recording Using Common-Mode Charge Pump for Robust 20-VPP Common-Mode Interference

A low-noise and -power readout integrated circuit (IC) for two-electrode electrocardiogram (ECG) recording is developed in this study using a common-mode charge pump (CMCP) for a robust 20-VPP common-mode interference (CMI). Two-electrode ECG recording offers more comfort than three-electrode ECG recording. Contrasting to the three-electrode ECG recording, the two-electrode ECG recording is affected by CMI during measurements; the intervention of a large CMI will distort the ECG signal measurement. To achieve robustness for the CMI, the proposed ECG readout IC adopts CMCP—it uses switched capacitors that store and subtract CMI by control logic. In this paper, a window comparator structure is applied to CMCP to obtain a signal with less distortion. The window voltage ranges were set between the input common-mode ranges in which IA can operate. Therefore, a signal with less distortion was obtained by stopping the operation of CMCP between the window voltage ranges. It also reduced additional current consumption. To achieve this, the proposed circuit is implemented using a chopper stabilization technique. The chopper implemented in the amplifier can reduce low-frequency noise components, such as 1/f noise, and it comprises a CMCP, current feedback instrumentation amplifier, QRS peak detector, relaxation oscillator, voltage reference, timing generator, and serial peripheral interface on a single chip. The proposed circuit was designed using a standard 0.18 μm CMOS process with an active area of 0.54 mm2. The proposed CMCP achieves a CMI robustness of 20 VPP at 60 Hz. The measured input-referred noise level was 119 nV/√Hz at 1 Hz, and the power consumption was 23.83 μW with a 1.8 V power supply.