Input-referred Noise Density Research Articles

A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes

A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude modulation (4-PAM) with −8.2-dBm sensitivity is presented in support for optical receivers required in the next-generation intra-data center links. A proposed three-stage TIA is comprised of a shunt-feedback stage followed by digitally programmable continuous-time linear equalizers (CTLEs) and a variable gain amplifier (VGA). Broadband low-noise design is achieved by having the first stage with much lower bandwidth (BW) followed by the proposed BW recovering CTLEs. A low-power design is supported by the inverter-based single-ended architecture with a single-ended-to-pseudo-differential conversion in the last stage. TIA’s BW extension is further supported by optimizing the photodiode-to-receiver (PD-to-RX) interconnect and utilizing several inductive peaking techniques. It achieves 63-dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> gain, 32-GHz BW, and an average input-referred current noise density of 16.9 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sqrt {\text {Hz}}$ </tex-math></inline-formula> while operating at 0.9-V supply and consuming 47-mW power. Opto-electrical measurements are performed on a co-packaged prototype comprised of identical proposed TIAs in CMOS with combinations of various commercial PDs and PD-to-RX interconnect lengths confirming 112-Gb/s 4-PAM reception meeting pre-forward error correction (FEC) symbol error rate (SER) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.8 \times 10 ^{-4}$ </tex-math></inline-formula> without any post-equalization.

A strip line technique based 1 Gb/s, 70-dB linear dynamic range transimpedance amplifier towards LiDAR unmanned vehicle application

1This work reports a Microstrip Line (MSL) based Dual-Gate MOSFET (DGMOSFET) Transimpedance amplifier (TIA) for LIDAR unmanned vehicle application under different weather conditions. TIA (Design-I) is proposed under normal weather, while TIA (Design-II) for foggy weather conditions. TIA (Design-I) employs a variable gain common gate topology with post-amplification, resulting in high gain, wide bandwidth, and high dynamic range (DR). TIA (Design-II) incorporates a series MSL section at the input of TIA (Design-I), which further enhances the bandwidth performance. TIA (Design-I) realizes a fractional bandwidth of 104.3% with a transimpedance gain of 100.4 dBΩ and low input-referred noise (IRN) density of 4.29 pA/√Hz. TIA (Design-II) achieves a fractional bandwidth of 178.4% with transimpedance gain, IRN, and DR of 100.42 dBΩ, 3.81 pA/√Hz, and 70 dB, respectively. TIA (Design-II) demonstrates a 1 Gb/s data rate with a bit-error-rate < 10−10. The TIA (Design-I) and TIA (Design-II) consume the power of 33 mW and 39 mW under the supply voltage of 2 V.

A Wideband Noise and Harmonic Distortion Canceling Low-Noise Amplifier for High-Frequency Ultrasound Transducers.

This paper presents a wideband low-noise amplifier (LNA) front-end with noise and distortion cancellation for high-frequency ultrasound transducers. The LNA employs a resistive shunt-feedback structure with a feedforward noise-canceling technique to accomplish both wideband impedance matching and low noise performance. A complementary CMOS topology was also developed to cancel out the second-order harmonic distortion and enhance the amplifier linearity. A high-frequency ultrasound (HFUS) and photoacoustic (PA) imaging front-end, including the proposed LNA and a variable gain amplifier (VGA), was designed and fabricated in a 180 nm CMOS process. At 80 MHz, the front-end achieves an input-referred noise density of 1.36 nV/sqrt (Hz), an input return loss (S11) of better than −16 dB, a voltage gain of 37 dB, and a total harmonic distortion (THD) of −55 dBc while dissipating a power of 37 mW, leading to a noise efficiency factor (NEF) of 2.66.

A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/f noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> ) same as the sampling frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> ). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/ √{Hz} input-referred noise density, 1.9 μV offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> . With -110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique.

An Active Concentric Electrode for Concurrent EEG Recording and Body-Coupled Communication (BCC) Data Transmission.

This paper presents a wearable active concentric electrode for concurrent EEG monitoring and Body-Coupled Communication (BCC) data transmission. A three-layer concentric electrode eliminates the usage of wires. A common mode averaging unit (CMAU) is proposed to cancel not only the continuous common-mode interference (CMI) but also the instantaneous CMI of up to 51Vpp. The localized potential matching technique removes the ground electrode. An open-loop programmable gain amplifier (OPPGA) with the pseudo-resistor-based RC-divider block is presented to save the silicon area. The presented work is the first reported so far to achieve the concurrent EEG signal recording and BCC-based data transmission. The proposed chip achieves 100dB CMRR and 110dB PSRR, occupies 0.044 mm2, and consumes 7.4μW with an input-referred noise density of 26nV/√Hz.

Low-Noise Si-JFETs Enhanced by Split-Channel Concept

We present the results of low-noise silicon junction field-effect transistors (JFET) with a split-channel concept. The device can be manufactured as a module in a standard CMOS process. The channel is split under the top gate of the JFET into a source-side main channel and a drain-side-extended drain channel. Devices with design gate length between 1.0 and 3.0 μm and effective channel length between 0.1 and 2.2 μm were fabricated. It is shown that transconductance and channel resistance are dominated by the overlap between the main channel and the top gate. Output resistance can be enhanced by increasing the overlap of the extended drain channel with the top gate. A cutoff frequency of up to 2.5 GHz, 60-mS/mm maximum transconductance, and an intrinsic gain of 2200 were achieved. For the main channel length below 1 μm, a strong roll-off behavior of the threshold voltage is observed. The flicker-corner frequency for 1/f noise is 500 Hz. Above 1 kHz, √ a value of 2.5-nV/ Hz input-referred voltage noise density at 0.3-pF input capacitance was achieved. Also, a brief comparison to devices from other publications is presented.

A 0.3 lx–1.4 Mlx Monolithic Silicon Nanowire Light-to-Digital Converter With Temperature-Independent Offset Cancellation

This article presents a monolithic light-to-digital converter (LDC) based on silicon nanowires. The silicon nanowires are arranged in a configuration, which allows cancellation for the offset due to dark leakage current and facilitates system-level chopping of the signal chain, including the nanowires. The readout integrated circuit (ROIC) has an analog front end (AFE) with a resistive-feedback transimpedance amplifier (TIA) to provide a constant voltage that strongly biases the nanowires. A programmable-gain switched-capacitor incremental delta–sigma analog-to-digital converter doubles the output of the TIA and feeds a digital back end that provides a decimated output. Finally, system-level chopping reduces the residual offset and 1/ ${f}$ noise, and 50-/60-Hz rejection suppresses interference from mains lighting. Fabricated in a 0.18- $\mu \text{m}$ CMOS process, the LDC has an input-referred current noise density of 235 fA/ $\surd $ Hz, and a dynamic range of 106.7, from 0.3 lx to 1.4 Mlx. The offset from the nanowires and the AFE is reduced to less than 30 $\mu \text{V}$ and offset drift of 193 nV/°C in a temperature range of −40 °C–85 °C. The AFE of the LDC draws 59.5 $\mu \text{A}$ at 3.3 V, and the digital back end draws $8~\mu \text{A}$ at 1.8 V.

Transimpedance amplifiers with 133 GHz bandwidth on 130 nm indium phosphide double heterojunction bipolar transistors

In this work, the authors present two transimpedance amplifier (TIA) circuits designed for fibre optical interconnect systems. They compare a common base (CB) topology with a common emitter (CE) shunt shunt feedback topology in terms of frequency response, power consumption, noise, and input impedance. The two TIAs are designed on a 130 nm indium phosphide double heterojunction bipolar transistor technology from Teledyne Scientific Company (TSC) with an 1 f(t)/f(max). of 520 GHz/1.15 TED and are measured in the frequency and time domains. They exhibit a transimpedance gain of 42 dBS2 with a 133 GHz bandwidth, the highest bandwidth reported in the literature and power consumption of 32.3 nikV tqr the C13 and 25.5 mW for the CE. Eye diagram measurements were conducted up to 64 Ghps and input referred noise density was measured at 30.2 pAh/root Hz for the CB and 13.9 pA.root Hz for the CE.

34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers

High spectral efficiency offered by the coherent optical communication links makes them attractive for the next-generation optical communication links. Using advanced modulation schemes such as dual-polarization quadrature-amplitude modulation (DP-QAM) data rates beyond 200 Gb/s can be achieved. A key component of such links is the wide-bandwidth and high-linearity coherent optical receiver. In this paper, we present a fully differential (FD) optical receiver architecture consisting of a variable-gain transimpedance amplifier (VG-TIA) followed by a VG amplifier (VGA). The proposed optical receiver employs a dual-feedback automatic gain control (AGC) loop that controls both the front-end VG-TIA and the following VGA to achieve both low-noise and high-linearity operation. A new photodiode (PD) dc current cancellation scheme is developed and implemented for the full differential front-end TIA. A prototype dual-TIA chip is fabricated in a 0.13- $\mu \text{m}$ SiGe BiCMOS process. The presented TIA achieves 20-pA/ $\sqrt {\text {Hz}}$ input-referred noise (IRN) density, 27-GHz, 3-dB bandwidth, and 1.5% total harmonic distortion (THD) at 1-mApp input PD current and 500-mVpp output voltage swing. This enables the 34-GBd operation with the bit error rate (BER) of $10^{-10}$ and $5.4\times 10^{-4}$ using DP-QPSK and DP-16-QAM formats at optical signal-to-noise ratios (OSNRs) of 25 and 30 dB, respectively, demonstrating the 100- and 200-Gb/s single wavelength optical coherent receiver operation. The dual-TIA chip occupies an area of $1.4\,\,\text {mm}\times 1.6$ mm and consumes 313 mW per channel at 34 GBd from a 3.3-V supply.

An Energy-Efficient 3.7-nV/&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\surd$ &lt;/tex-math&gt; &lt;/inline-formula&gt;Hz Bridge Readout IC With a Stable Bridge Offset Compensation Scheme

This paper describes an energy-efficient bridge readout IC (ROIC), which consists of a capacitively coupled instrumentation amplifier (CCIA) that drives a continuous-time delta–sigma modulator (CT $\Delta \Sigma \text{M}$ ). By exploiting the CCIA’s ability to block dc common-mode voltages, the bridge’s bias voltage may exceed the ROIC’s supply voltage, allowing these voltages to be independently optimized. Since bridge output is typically much smaller than bridge offset, a digital to analog converter (DAC) is used to compensate this offset before amplification and thus increase the CCIA’s useful dynamic range. Bridge loading is reduced by using a dual-path positive feedback scheme to boost the CCIA’s input impedance. Furthermore, the CCIA’s output is gated to avoid digitizing its output spikes, which would otherwise limit the ROIC’s linearity and stability. The ROIC achieves an input-referred noise density of 3.7 nV/ $\surd $ Hz, a noise efficiency factor (NEF) of 5, and a power efficiency factor (PEF) of 44, which both represent the state of the art. A pressure sensing system, built with the ROIC and a differential pressure sensor (AC4010), achieves 10.1-mPa ( $1\sigma$ ) resolution in a 0.5-ms conversion time. The ROIC dissipates about 30% of the system’s power dissipation and contributes about 6% of its noise power. To reduce the sensor’s offset drift, a temperature compensation scheme based on an external reference resistor is used. After a two-point calibration, this scheme reduces bridge offset drift by $80\times $ over a 50 °C range.

Fully‐differential second‐order tunable bandstop filter based on source follower

A new design method for a second-order bandstop filter is presented. The proposed filter is based on the source follower configuration with a partial positive feedback. The positive feedback is used to increase the quality factor of the filter, and the feed-forward paths are used to create complex zeros. The proposed bandstop filter has electronically tunable centre frequency, bandwidth and attenuation with low power consumption. The proposed design has been simulated in TSMC 180 nm CMOS technology. The filter achieves 5.8 nV / Hz input-referred noise density. For a 2 GHz input signal, the filter achieves a signal-to-noise ratio of 60 dB for 238 mV 0 − P , diff input signal amplitude. The simulated results show that the centre frequency tuning range is between 1.6 and 3 GHz and the bandwidth is tunable from 0.6 to 1 GHz. The filter consumes about 2.5 mW for a supply voltage of 1.8 V at a centre frequency of 2.3 GHz.

High Sensitivity and Wide Dynamic Range Analog Front-End Circuits for Pulsed TOF 4-D Imaging LADAR Receiver

Analog front-end (AFE) circuits, which mainly consist of a transimpedance amplifier (TIA) with wide dynamic range and a timing discriminator with double threshold voltage, were designed and implemented for a pulsed time-of-fight 4-D imaging LADAR receiver. The preamplifier of the proposed TIA adopts a shunt-feedback topology to amplify weak echo signal, and a current-mirror topology to amplify strong one, respectively. The proposed AFE can capture directly the pulsed echo amplitude with wide dynamic range through programmable gain control switches. The proposed AFE circuits, which achieve a high gain of 106 dB $\Omega $ , a linear dynamic range of 80 dB, an averaged input-referred noise density of 0.89 pA/Hz0.5 and a minimum detectable signal of $0.36~\mu \text{A}$ at SNR = 5, and a sensitivity of 8 nW with APD of 45 A/W, were designed with 3.3 V devices and fabricated in a 0.18- $\mu \text{m}$ standard CMOS process. The total area of AFE, which includes the circuit core, bandgap and bias circuits, and I/O PAD, is approximately equal to $1.20\times 1.13$ mm2.

100 Gb/s Differential Linear TIAs With Less Than 10 pA/ $\sqrt {\mathrm {Hz}}$ in 130-nm SiGe:C BiCMOS

The design methodology and circuit implementation of a transimpedance (TI) amplifier (TIA) featuring low averaged input-referred current noise density without compromising the TIA bandwidth (BW) are presented. The technology role in the key performance metrics is also discussed and verified by means of two analogous TIA designs implemented in two different 130-nm SiGe:C BiCMOS processes from IHP, SG13S with $f_{T}/f_{\max }= 250/340$ GHz and SG13G2 with $f_{T}/f_{\max }= 300/500$ GHz. Both TIAs adopt a fully differential linear architecture with three stages: an input shunt-feedback TI stage followed by a variable gain amplifier which provides post-amplification with 15-dB gain control range and an output 50- $\Omega $ buffer. The TIA in SG13S features 68.5 dB $\Omega $ differential TI gain, 42-GHz 3-dB BW, and 8 pA/ $\sqrt {\mathrm {Hz}}$ averaged input-referred current noise density while the second TIA in SG13G2 provides 65 dB $\Omega $ differential TI gain, 66-GHz 3-dB BW, and 7.6 pA/ $\sqrt {\mathrm {Hz}}$ . Measured total harmonic distortion in both TIAs in the maximum gain condition is better than 5% for ~800 mVppd output swing and input currents of ~300 $\mu $ App. Both circuits dissipate 150 mW of power and are shown to operate at up to 100 Gb/s data rate with clean PRBS31 non-return to zero and PAM-4 eye diagrams. To the author’s best knowledge, the reported TIAs exhibit the lowest averaged input-referred current noise density shown to date at a BW sufficient to support 100 Gb/s net data rate, surpassing other silicon-based and InP implementations toward the next-generation 400 Gb/s optical links.

A DC-75-GHz Bandwidth and 54 $\text {dB}\Omega $ Gain TIA With 10.9 pA/ $\sqrt {\mathrm {Hz}} $ in 130-nm SiGe:C BiCMOS

A broadband low-noise amplifier with transimpedance (TI) feedback implemented in a 130-nm SiGe:C BiCMOS technology with $f_{T}$ of 300 GHz is presented. The circuit provides 22-dB gain and 75-GHz bandwidth while dissipating only 95 mW of power, achieving a gain bandwidth against dc power efficiency (GBW/ $P_{\mathrm {dc}}$ ) of 9.9 GHz/mW. Measured noise figure (NF) is 4 dB until 26.5 GHz, rising up to 6 dB at 70 GHz based on simulation. Ultrahigh data rate support is demonstrated with clear eye diagrams up to 100 Gb/s. Intended as a TI front end for optical receivers, the amplifier features 54- $\text {dB}\Omega $ TI gain with only 10.9 pA/ $\sqrt {\mathrm {Hz}}$ averaged input-referred current noise density. Measured input-referred 1-dB compression point at 1 GHz occurs at −20 dBm input power. To the best of the authors’ knowledge, the proposed amplifier exhibits the highest GBW/ $P_{\mathrm {dc}}$ with the lowest NF reported to date, toward the next generation 400 Gb/s Ethernet.

Low-Power ${G}_{{m}}{-}C$ Filter Employing Current-Reuse Differential Difference Amplifiers

This paper deals with the design of low-power high-performance continuous-time filters. The proposed operational transconductance amplifier architecture employs current-reuse differential difference amplifiers in order to produce more power-efficient ${G}_{{m}}{-}{C}$ filter solutions. To demonstrate this, a sixth-order low-pass Butterworth filter was designed in a 0.18- $\mu\text{m}$ CMOS, achieving a 65-MHz −3-dB frequency, an in-band input-referred third-order intercept point of 12 dBm, and an input-referred noise density of 40 nV/Hz1/2, while only consuming 8.07 mW from a 1.8-V supply and occupying a total chip area of 0.21 mm2 with a power consumption of only 1.19 mW per pole.

Low-Power Low-Noise Amplifier Using Attenuation-Adaptive Noise Control for Ultrasound Imaging Systems

This paper presents a low-noise amplifier (LNA) using attenuation-adaptive noise control (AANC) for ultrasound imaging systems. The proposed AANC reduces unnecessary power consumption of the LNA, which arises from useless noise floor, by controlling the noise floor of the LNA with respect to the attenuation of the ultrasound. In addition, a current feedback amplifier with a source-degenerated input stage reduces variations of the bandwidth and the closed loop gain, which are caused by the AANC. The proposed LNA was fabricated using a 0.18-[Formula: see text] CMOS process. The input-referred voltage noise density of the fabricated LNA is 1.01 [Formula: see text] at the frequency of 5 MHz. The second harmonic distortion is -53.5 dB when the input signal frequency is 5 MHz and the output voltage swing is 2 [Formula: see text]. The power consumption of the LNA using the AANC is 16.2 mW at the supply voltage of 1.8 V, which is reduced to 64% of that without using the AANC. The noise efficiency factor (NEF) of the proposed LNA is 3.69, to our knowledge, which is the lowest NEF compared with previous LNAs for ultrasound imaging.

A 50- to 300-MHz CMOS &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$Gm\mbox{-}C$&lt;/tex-math&gt;&lt;/inline-formula&gt; Tracking Filter Based on Parallel Operation of Saturation and Triode Transconductors for Digital TV Tuner ICs

In this brief, a 50- to 300-MHz CMOS Gm-C tracking low-pass filter has been presented to resolve a LO harmonic-mixing problem for Advanced Television Systems Committee terrestrial and cable digital TV tuner integrated circuits. A Gm-C filter based on parallel operation of a transconductor biased in the saturation region with source degeneration and a transconductor biased in the triode region is chosen to achieve high linearity performance at the very high frequency/ultrahigh frequency bands. The cutoff frequency of the proposed filter is tunable from 50 to 300 MHz. The filter is implemented in a 0.18-μm CMOS technology and achieves a minimum input-referred noise density of 3 nV/√Hz and maximum in-band output-referred third-order intercept point of 20.7 dBm. It operates at a nominal supply voltage of 1.8 V with bias currents of 114 mA. The active die area is 1.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A CMOS Power-Efficient Low-Noise Current-Mode Front-End Amplifier for Neural Signal Recording

In this paper, a new current-mode front-end amplifier (CMFEA) for neural signal recording systems is proposed. In the proposed CMFEA, a current-mode preamplifier with an active feedback loop operated at very low frequency is designed as the first gain stage to bypass any dc offset current generated by the electrode-tissue interface and to achieve a low high-pass cutoff frequency below 0.5 Hz. No reset signal or ultra-large pseudo resistor is required. The current-mode preamplifier has low dc operation current to enhance low-noise performance and decrease power consumption. A programmable current gain stage is adopted to provide adjustable gain for adaptive signal scaling. A following current-mode filter is designed to adjust the low-pass cutoff frequency for different neural signals. The proposed CMFEA is designed and fabricated in 0.18-μm CMOS technology and the area of the core circuit is 0.076 mm(2). The measured high-pass cutoff frequency is as low as 0.3 Hz and the low-pass cutoff frequency is adjustable from 1 kHz to 10 kHz. The measured maximum current gain is 55.9 dB. The measured input-referred current noise density is 153 fA /√Hz , and the power consumption is 13 μW at 1-V power supply. The fabricated CMFEA has been successfully applied to the animal test for recording the seizure ECoG of Long-Evan rats.

Accurate dB-Linear Variable Gain Amplifier With Gain Error Compensation

This paper describes use of a novel exponential approximation for designing dB-linear variable gain amplifiers (VGAs). The exponential function is accurately generated using a simple error-compensation technique. The dB-linear gain is controlled linearly by the gate voltage, resulting in a simple and robust VGA. The proposed dB-linear VGA fabricated in a 65-nm CMOS process achieves a total variable gain range of 76 dB and dB-linear range greater than 50 dB with ±0.5-dB gain error. Under a 1.2-V supply voltage, the current consumption of the VGA is 1.8 mA and that of the output buffer is 1.4 mA. The input-referred in-band noise density is 3.5 nV/√{Hz} and the in-band OIP3 is 11.5 dBm. Due to the very simple circuit topology, the total active area of the VGA and the output buffer is extremely small, 0.01 mm2.

Analog baseband chain of synthetic aperture radar (SAR) receiver

An analog baseband chain for a synthetic aperture radar receiver implemented in a 130 nm CMOS technology is presented in this paper. Occupying 0.23 mm2 of silicon area, the baseband chain consists of a three-stage variable gain amplifier (VGA), a 5th-order gm-C low-pass filter (LPF) and an output buffer. The gain of the chain can be controlled by tuning the control voltages of the VGA and has a range from 25 to 34 dB. 8 dB of the gain is embedded into the LPF. The bandwidth of the LPF is programmable from 100 to 190 MHz by means of capacitor matrices. The chain, which uses a 1.2 V supply voltage, achieves an input-referred noise density of 4 nV/ $$ \sqrt {\text{Hz}} $$ and an in-band IIP3 of ?46 dBV rms.