A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs

Abstract

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/f noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> ) same as the sampling frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> ). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/ √{Hz} input-referred noise density, 1.9 μV offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> . With -110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique.