100 Gb/s Differential Linear TIAs With Less Than 10 pA/ $\sqrt {\mathrm {Hz}}$ in 130-nm SiGe:C BiCMOS

Abstract

The design methodology and circuit implementation of a transimpedance (TI) amplifier (TIA) featuring low averaged input-referred current noise density without compromising the TIA bandwidth (BW) are presented. The technology role in the key performance metrics is also discussed and verified by means of two analogous TIA designs implemented in two different 130-nm SiGe:C BiCMOS processes from IHP, SG13S with $f_{T}/f_{\max }= 250/340$ GHz and SG13G2 with $f_{T}/f_{\max }= 300/500$ GHz. Both TIAs adopt a fully differential linear architecture with three stages: an input shunt-feedback TI stage followed by a variable gain amplifier which provides post-amplification with 15-dB gain control range and an output 50- $\Omega $ buffer. The TIA in SG13S features 68.5 dB $\Omega $ differential TI gain, 42-GHz 3-dB BW, and 8 pA/ $\sqrt {\mathrm {Hz}}$ averaged input-referred current noise density while the second TIA in SG13G2 provides 65 dB $\Omega $ differential TI gain, 66-GHz 3-dB BW, and 7.6 pA/ $\sqrt {\mathrm {Hz}}$ . Measured total harmonic distortion in both TIAs in the maximum gain condition is better than 5% for ~800 mVppd output swing and input currents of ~300 $\mu $ App. Both circuits dissipate 150 mW of power and are shown to operate at up to 100 Gb/s data rate with clean PRBS31 non-return to zero and PAM-4 eye diagrams. To the author’s best knowledge, the reported TIAs exhibit the lowest averaged input-referred current noise density shown to date at a BW sufficient to support 100 Gb/s net data rate, surpassing other silicon-based and InP implementations toward the next-generation 400 Gb/s optical links.