Input-referred Noise Density Research Articles

Low-Power SiGe BiCMOS Transimpedance Amplifier for 25-GBaud Optical Links

We propose a new circuit for the realization of transimpedance amplifiers (TIAs), targeted at reducing the input-referred noise of the TIA or alternatively increasing the bandwidth, without increasing the power dissipation. An intensive theoretical analysis of the method is given. A prototype chip is fabricated in 0.25- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula> SiGe BiCMOS technology. The TIA has a gain of 71 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{dB}\Omega$</tex></formula> , a bandwidth of 20.5 GHz, and an average input-referred current noise density of 18 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{pA}/\surd \hbox{Hz}$</tex> </formula> . The circuit operates from a 2.5-V supply, and power dissipation is 57 mW.

Low-power low-noise analog signal conditioning chip with on-chip drivers for healthcare applications

This paper presents an ultra low-noise, low-voltage complete analog signal conditioning chip, fabricated in 180nm mixed-mode CMOS process. In contrast to many already-reported biomedical chips the test chip has been fabricated in a relatively scaled technology operating at low supply voltage of 1.8V. This enables targeting energy-efficient hand-held biomedical devices where low-noise analog signal conditioning, preliminary processing and low-power wireless functionalities will be integrated on one chip. The test chip features instrumentation amplifier (INA) with chopper modulation at the first stage. The second stage is a novel area efficient spike removal filter (SRF) for attenuating coupled chopping spikes. The last stage is a differential active RC filter to adjust gain and bandwidth of the forward channel. On-chip non-overlapping clock generators with frequency of 4kHz and 8kHz for SRF stage are also implemented on the test. The chip also features a reconfigurable driven-right-leg circuit (DRLC) and shield drive amplifier (SDA) in the feedback path specifically for portable healthcare instruments. The DRLC provides the feedback either with operational amplifier (op-amp) or operational transconductance amplifier (OTA), configurable by the user. The presented test chip, for the first time, demonstrates an integrated OTA-based DRLC along with INA. INA and drivers have been designed and optimized for minimum power dissipation using a power-oriented design flow. The measurement results show that the INA achieves input-referred noise density of 28nv/Hz and DC current of 5.9μA maintaining minimum of 109dB at 1.91kHz. Measurements also show that 34dB interference reduction at 50Hz is achieved with DRLC. Low operating voltage, wide range of specifications and reconfigurable modules and interconnections enable the chip to be used for broad range of signal conditioning applications.

A Multichannel Integrated Circuit for Electrical Recording of Neural Activity, With Independent Channel Programmability

Since a few decades, micro-fabricated neural probes are being used, together with microelectronic interfaces, to get more insight in the activity of neuronal networks. The need for higher temporal and spatial recording resolutions imposes new challenges on the design of integrated neural interfaces with respect to power consumption, data handling and versatility. In this paper, we present an integrated acquisition system for in vitro and in vivo recording of neural activity. The ASIC consists of 16 low-noise, fully-differential input channels with independent programmability of its amplification (from 100 to 6000 V/V) and filtering (1-6000 Hz range) capabilities. Each channel is AC-coupled and implements a fourth-order band-pass filter in order to steeply attenuate out-of-band noise and DC input offsets. The system achieves an input-referred noise density of 37 nV/√Hz, a NEF of 5.1, a CMRR > 60 dB, a THD < 1% and a sampling rate of 30 kS/s per channel, while consuming a maximum of 70 μA per channel from a single 3.3 V. The ASIC was implemented in a 0.35 μm CMOS technology and has a total area of 5.6 × 4.5 mm². The recording system was successfully validated in in vitro and in vivo experiments, achieving simultaneous multichannel recordings of cell activity with satisfactory signal-to-noise ratios.

A 40-Gb/s Optical Transceiver Front-End in 45 nm SOI CMOS

A low-power, 40-Gb/s optical transceiver front-end is demonstrated in a 45-nm silicon-on-insulator (SOI) CMOS process. Both single-ended and differential optical modulators are demonstrated with floating-body transistors to reach output swings of more than 2 VPP and 4 VPP, respectively. A single-ended gain of 7.6 dB is measured over 33 GHz. The optical receiver consists of a transimpedance amplifier (TIA) and post-amplifier with 55 dB ·Ω of transimpedance over 30 GHz. The group-delay variation is ±3.9 ps over the 3-dB bandwidth and the average input-referred noise density is 20.5 pA/(√Hz) . The TIA consumes 9 mW from a 1-V supply for a transimpedance figure of merit of 1875 Ω /pJ. This represents the lowest power consumption for a transmitter and receiver operating at 40 Gb/s in a CMOS process.

A GAIN/FILTERING INTERLEAVED BASEBAND CHAIN ARCHITECTURES FOR MULTISTANDARD RECONFIGURABLE RECEIVERS

In this paper, four baseband chain architectures used in multistandard (UMTS–WLAN) reconfigurable receivers will be introduced, simulated and, compared. The architectures are realized using 0.25 μm CMOS technology operating with 1.2 V supply voltage. The baseband chain consists of three stages: the first and the last stage are programmable gain amplifiers and the intermediate stage is an active Gm-RC LPF filter. The proposed architectures are compared in terms of DC-gain, noise, linearity, SFDR, and power consumption. The best receiver architecture is then derived based on system level analysis and based on a defined figure-of-merit. The best baseband chain bandwidth is controlled by the active Gm-RC filter with a value 2.2 MHz for UMTS and 11 MHz for WLAN. The baseband gain can be programmed in the range of -6÷68 dB, while the input-referred noise density is less 20 nV/√Hz for UMTS and 25 μV/√Hz for WLAN.

A 23.4 mW 68 dB Dynamic Range Low Band CMOS Hybrid Tracking Filter for ATSC Digital TV Tuner Adopting RC and Gm-C Topology

In this paper, a 48-200 MHz CMOS hybrid tracking low-pass filter with low power and high dynamic range is presented to solve a local oscillator harmonic-mixing problem for Advanced Television Systems Committee terrestrial digital TV tuner integrated circuits. For low power consumption, the first-order passive RC filter and the second-order transconductor-C filter are combined to implement the third-order Chebyshev tracking low-pass filter. A transconductor linearization technique based on a method of multiple gated transistors is adopted to achieve high dynamic range. Fabricated in a 0.18 μm CMOS process, it achieves a maximum in-band input-referred noise density of 5.1 nV/√Hz and maximum in-band output-referred third-order intercept point of 17.3 dBm, while dissipating 23.4 mW with 1.8 V. The total chip area is 0.6 mm × 0.4 mm.

An integrated low-voltage ultra-low-power reconfigurable hardware interface in 0.18-µm CMOS

This article presents an interface application specific integrated circuit (ASIC) adaptable to a wide range of bio- and neuro-signal applications. The chip consists of a low-noise analogue front end (FE) and a successive-approximation analogue-to-digital converter (ADC). The entire analogue signal processing chain is fully differential for better immunity to common mode noise and interferences. To make the interface adaptable to different biopotential signals, the bandwidth and gain of the analogue FE are configurable. The ADC is designed for rail-to-rail operation and the input full-scale is adjustable so that the resolution requirement can be relaxed. Fabricated in 0.18-µm complementary metal oxide semiconductor (CMOS), input-referred noise density and more than 100-dB CMRR are obtained. Operating in a 10-bit mode, the ADC exhibits −1/+0.3-LSB DNL and −1.3/+0.8-LSB INL least significant bit integral nonlinearity for 1-V rail-to-rail input. The whole interface integrated circuit (IC) consumes 36 µW from a single 1-V supply, making it suitable for a wide range of low-voltage and low-power bio- and neuro-chip platforms.

A Low Power and Low Noise On-Chip Active RF Tracking Filter for Digital TV Tuner ICs

In this paper, a highly linear and low noise CMOS active RF tracking filter for a digital TV tuner is presented. The Gm cell of the Gm-C filter is based on a dynamic source degenerated differential pair with an optimized transistor size ratio, thereby providing good linearity and high-frequency operation. The proposed RF tracking filter architecture includes two complementary parallel paths, which provide harmonic rejection in the low band and unwanted signal rejection in the high band. The fabricated tracking filter based on a 0.13µm CMOS process shows a 48∼860MHz tracking range with 30-32dB 3rd order harmonic rejection, a minimum input referred noise density of 2.4nV/√Hz, and a maximum IIP3 of 0dBm at 3dB gain while drawing 39mA from a 1.2-V supply. The total chip area is 1mm × 0.9mm.

A universal low-noise analog receiver baseband in 65-nm CMOS

In this paper, a novel universal receiver baseband approach is introduced. The chain includes a post-mixer noise shaping blocker pre-filter, a programmable-gain post mixer amplifier (PMA) with blocker suppression, a differential ramp-based novel linear-in-dB variable gain amplifier and a Sallen---Key output buffer. The 1.2-V chain is implemented in a 65-nm CMOS process, occupying a die area of 0.45 mm2. The total power consumption of the baseband chain is 11.5 mW. The device can be tuned across a bandwidth of 700-KHz to 5.2-MHz with 20 kHz resolution and is tested for two distinct mobile-TV applications; integrated services digital broadcasting-terrestrial ISDB-T (3-segment f c = 700 kHz) and digital video broadcasting-terrestrial/handheld (DVB-T/H f c = 3.8 MHz). The measured IIP3 of the whole chain for the adjacent blocker channel is 24.2 and 24 dBm for the ISDB-T and DVB-T/H modes, respectively. The measured input-referred noise density is 10.5 nV/sqrtHz in DVB-T/H mode and 14.5 nV/sqrtHz in ISDB-T mode.

Noise-Shaping Gain-Filtering Techniques for Integrated Receivers

In this paper, a new technique for realizing area-efficient, low-noise filters is introduced. The proposed filter topologies utilize noise shaping techniques to shift the noise of the passive and active filter components out of the passband of the filter. This is illustrated by implementing a programmable noise-shaped post-mixer gain-filtering circuit for a CMOS Mobile-TV tuner. The proposed circuits relax the noise-linearity tradeoff in the receiver chain by providing blocker rejection following the mixer outputs. The filter provides an in-band input referred noise density as low as 7.5 nV/sqrt(Hz). The measured out-of-band IIP3 values are 30 dBV and 31.5 dBV for the 3.8-MHz (DVB-H) and 750-kHz (ISDB-T) modes, respectively. Total current consumption is 5.5 mA from a 1.2-V supply. The gain of the block is programmable to be 0 dB, 8ndB, 14 dB, or 20 dB. The design occupies a die area of 0.28 mm2 in a 65-nm CMOS process covering a frequency band of 700 kHz to 5.2 MHz as a universal mobile-TV integrated baseband gain-filtering solution.

A Differential-Ramp Based 65 dB-Linear VGA Technique in 65 nm CMOS

In this paper, a differential-ramp based variable gain amplifier (VGA) technique is introduced. Using the proposed technique, digitally programmable gain amplifiers (PGAs) can be converted to analog controlled, dB-linear VGAs with minimum impact on noise and linearity. This provides an efficient way of realizing an analog controlled VGA for OFDM based applications. The technique is illustrated by converting an opamp based high-linearity, low-noise PGA to a dB-linear VGA for CMOS mobile TV applications. The design including the cascade of a two-stage continuous 65-dB-linear VGA and a third-order Sallen-Key buffer stage is fabricated in a 65 nm CMOS process. The measured in-band OIP3 of the whole chain at maximum gain of 47 dB is 22 dBm, whereas the blockers in the adjacent channel result in 34 dBm OIP3 for the same gain setting. The design achieves 11 nV/?(Hz) input referred noise density and occupies a die area of 0.17 mm2. The VGA circuit consumes 1.5 mA of current from a 1.2 V supply with an additional 200 ?A switch control ramp current from a 2.5 V supply.

A 240-MHz Low-Pass Filter With Variable Gain in 65-nm CMOS for a UWB Radio Receiver

An integrated fifth-order continuous-time low-pass filter for a WiMedia ultrawideband radio receiver is described in this paper. The prototype filter is realized with a passive pole at the filter input and a fourth-order leapfrog filter in which the gm-C technique with pseudodifferential transconductors is used. The transconductors do not include internal nodes, and they are designed to have a nominal 26-dB dc gain, of which process, voltage, and temperature variations are controlled by means of a negative resistance circuit. The losses of the low-dc-gain filter integrators are already taken into account in the filter synthesis. The passband edge frequency of the implemented filter is 240 MHz in order to receive multiband-orthogonal-frequency-division-multiplexing signals using the direct-conversion topology. The voltage gain of the filter can be controlled from 9 to 43 dB in the 1-dB gain steps. The filter achieves a 7.8-nVradicHz input-referred noise density, a -8-dBV out-of-band third-order intermodulation intercept point, and a +15-dBV out-of-band second-order intermodulation intercept point. The circuit uses a 1.2-V supply and has been fabricated in a modern 65-nm CMOS technology.

A 50–300-MHz Highly Linear and Low-Noise CMOS $Gm{\hbox{-}}C$ Filter Adopting Multiple Gated Transistors for Digital TV Tuner ICs

In this paper, a highly linear and low noise CMOS active tracking low-pass filter is presented to overcome a local oscillator harmonic mixing problem for Advanced Television Systems Committee terrestrial and cable digital TV tuner integrated circuits. A transconductor linearization technique based on a method of multiple gated transistors is adopted to improve the linearity performance. The cutoff frequency of the proposed filter is tunable from 50 to 300 MHz. Fabricated in a 0.18-mum CMOS process, the filter provides a minimum input referred noise density of 5 nV/radic(Hz) and maximum in-band output referred third-order intercept point of 16.9 dBm, while drawing an average current of 40 mA from 1.8 V. The total chip area is 1 mm times 0.9 mm.

Design methodology of baseband analog chain to maximize a spurious free dynamic range for ATSC terrestrial and cable digital TV tuner

This paper presents a fully integrated tunable CMOS baseband analog (BBA) chain optimized for advanced television systems committee (ATSC) terrestrial and cable digital TV tuner integrated circuits (ICs). To maximize the spurious free dynamic range (SFDR) of the BBA chain for both standards, the design guideline is introduced with respect to the optimized allocation of the gain of each block. The bandwidth is selectable from 3 MHz, 3.5 MHz, or 4 MHz. Fabricated in a 0.18-mum CMOS process, it provides a minimum input referred noise density of 15.5 nV/radic(Hz) with 62 dB gain and out-of-channel output referred third-order intercept point (OIP3) of 33 dBm, while it drains an average current of 89 mA from 3.3 V. The total chip area is 1 mm times 1.2 mm.

Programmable SiGe BiCMOS low-pass filter for a multicarrier WCDMA base-station receiver

SiGe BiCMOS low-pass filter for a multicarrier WCDMA base-station receiver is described in this paper. The 4th-order Chebyshev filter with a 0.1-dB passband ripple is designed to drive a high-resolution A/D converter. The ?3-dB frequency of the implemented filter can be programmed to four different bandwidths: 2.5, 5, 7.5, and 10 MHz depending on the number of received WCDMA channels. The filter achieves +9.7-dBV in-band IIP3, +20-dBV out-of-band IIP3, and 8.5-nV/?Hz input-referred noise density with 10-MHz bandwidth. The circuit uses a 2.5 V supply and has been fabricated in a 0.25-μm SiGe BiCMOS process.

A 60 $\mu$W 60 nV/$\surd$Hz Readout Front-End for Portable Biopotential Acquisition Systems

There is a growing demand for low-power, small-size and ambulatory biopotential acquisition systems. A crucial and important block of this acquisition system is the analog readout front-end. We have implemented a low-power and low-noise readout front-end with configurable characteristics for Electroencephalogram (EEG), Electrocardiogram (ECG), and Electromyogram (EMG) signals. Key to its performance is the new AC-coupled chopped instrumentation amplifier (ACCIA), which uses a low power current feedback instrumentation amplifier (IA). Thus, while chopping filters the 1/f noise of CMOS transistors and increases the CMRR, AC coupling is capable of rejecting differential electrode offset (DEO) up to plusmn50 mV from conventional Ag/AgCl electrodes. The ACCIA achieves 120 dB CMRR and 57 nV/radicHz input-referred voltage noise density, while consuming 11.1 muA from a 3 V supply. The chopping spike filter (CSF) stage filters the chopping spikes generated by the input chopper of ACCIA and the digitally controllable variable gain stage is used to set the gain and the bandwidth of the front-end. The front-end is implemented in a 0.5 mum CMOS process. Total current consumption is 20 muA from 3V

A 0.18 μm CMOS direct down-converter for highly integrated 3G receivers

This paper presents the design of a high dynamic range direct down-converter for 3G cell-phone applications. The mechanisms responsible for second-order intermodulation distortion are discussed in details, leading to the following design strategy: the transconductor is degenerated by means of an RC filter, an LC network resonating at RF frequency loads the switching pair and carefully matched resistors are used in the output load. Prototypes realized in 0.18 μm CMOS show: +78 dBm IIP2 minimum among 40 samples, +10 dBm IIP3, 4 nV/?Hz input-referred noise density while burning only 4 mA from 1.8 V.

A High-Frequency Transconductor Using a Robust Nonlinearity Cancellation

This brief deals with the design of a linear operational transconductance amplifier (OTA) intended for high-frequency continuous-time filters. Three source-degenerated differential pairs are used to reduce the third-order distortion components regardless of process parameter tolerances and bias current. Experimental results for an OTA fabricated in the TSMC 0.35-mum CMOS process are presented and compared with recently reported topologies. Draining 2.8 mA from a single supply voltage of 3.3 V, the transconductor achieves IM3<-70 dB for a two-tone input signal of 1.3 Vpp measured at 70 MHz. The input referred noise density is only 7 nV/radicHz, leading to an SNR of 75 dB

High-gain differential CMOS transimpedance amplifier with on-chip buried double junction photodiode

An integrated fully differential CMOS transimpedance amplifier (TIA) with buried double junction photodiode input is described. The TIA features a variable high transimpedance gain (250 k/spl Omega/ to 2.5 M/spl Omega/), large DC photocurrent rejection capability (>55 dB) and low input referred noise density at 100 kHz (2pA//spl radic/Hz).

Robust highly linear high-frequency CMOS OTA with IM3 below - 70 dB at 26 MHz

An enhanced configuration for a linearized MOS operational transconductance amplifier (OTA) is proposed. The proposed fully differential OTA circuit is based on resistive source degeneration and an improved adaptive biasing technique. It is robust to process variation, which has not been fully shown in previously reported linearization techniques. Detailed harmonic distortion analysis demonstrating the robustness of the proposed OTA is introduced. The transconductance gain is tunable from 160 to 340 /spl mu/S with a third-order intermodulation (IM3) below -70 dB at 26 MHz. As an application, a 26-MHz second-order low-pass filter fabricated in TSMC 0.35-/spl mu/m CMOS technology with a power supply of 3.3 V is presented. The measured IM3 with an input voltage of 1.4 Vpp is below - 65 dB for the entire filter pass-band, and the input referred noise density is 156nV//spl radic/Hz. The cutoff frequency of the filter is tunable in the range of 13-26 MHz. Theoretical and experimental results are in good agreement.