InGaAs MOSFETs Research Articles

A novel technique exploiting C–V, G–V and I–V simulations to investigate defect distribution and native oxide in high-κ dielectrics for III–V MOSFETs

In this paper we present a novel defect spectroscopy technique to investigate the properties of high-κ metal-gate oxides. This technique, based on the simultaneous simulations of I–V, C–V and G–V curves at different frequencies, allows profiling the distribution of interfacial and bulk defects inside the gate oxide and investigating the composition of the high-κ stacks on III–V materials. The proposed technique is applied to investigate the properties of high-κ stacks of InGaAs MOSFETs.

Tunneling and Short Channel Effects in Ultrascaled InGaAs Double Gate MOSFETs

Full-band quantum transport simulations are performed to study the scaling of InGaAs MOSFETs. Short-channel effects evoke severe performance degradation in InGaAs MOSFETs and the tunneling leakage further deteriorates their performances. Reducing the body width is shown to suppress the short channel effects. Doping densities show big impacts on device performances. With inhomogeneous doping InGaAs could outperform Si at gate lengths below 15 nm with 5-nm body width. The density of state bottleneck does not affect InGaAs in simulated devices at 0.5 V supply voltage. At the ultrascaled dimensions the full band simulations are essential to capture strong nonparabolic dispersion. Comparison with a multivalley effective mass model shows that the population of higher conduction band valleys contributes to the total current at thin body widths.

Single-Event Transient Response of InGaAs MOSFETs

The single-event-transient response of InGaAs MOSFETs exposed to heavy-ion and laser irradiations is investigated. The large barrier between the gate oxide and semiconductor regions effectively suppresses the gate transients compared with other types of III-V FETs. After the initial radiation-induced pulse, electrons and holes flood into the channel region at short time. The electrons are collected efficiently at the drain. The slower moving holes accumulate in the channel and source access region and modulate the source-channel barrier, which provides a pathway for transient source-to-drain current lasting for a few nanoseconds. The peak drain transient current reaches its maximum when the gate bias is near threshold and decreases considerably toward inversion and slightly toward depletion and accumulation. Two-dimensional TCAD simulations are used to understand the charge collection mechanisms.

Ballistic Band-to-Band Tunneling in the OFF State in InGaAs MOSFETs

We present quantum transport simulation results for InAs and In 0.7 Ga 0.3 As double-gate MOSFETs by using an atomistic full-band basis to evaluate the tunneling currents in the OFF state. While InAs has the advantage of lower mass and higher injection velocity, it also has lower bandgap. For low gate bias, the overlap in energy of the valence band in the channel with the source/drain conduction bands results in band-to-band tunneling (BTBT) between source and drain, which clamps the OFF current. Such current can be reduced by increasing the bandgap of the material either by increasing confinement or by lowering the In content, for example, using In 0.7 Ga 0.3 As. Grading the doping of the source/drain region to create a wider barrier also reduces BTBT, but to a lesser extent.

Border Traps in InGaAs nMOSFETs Assessed by Low-Frequency Noise

The low-frequency noise of n-channel InGaAs MOSFETs with Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric has been studied to assess the impact of a S-passivation treatment on the border trap (BT) density. It is shown that the spectra are predominantly \(1/f\) -like, while the normalized noise power spectral density (PSD) behaves according to the number fluctuations theory. The BT density derived from the input-referred voltage noise PSD exhibits a flat depth profile for the three processing conditions studied, with a pronounced reduction due to the S treatment. Additional excess \(1/f\) and generation-recombination noise sources are found as well, which are more related to the epitaxial material.

(Invited) High κ/InGaAs for Ultimate CMOS – Interfacial Passivation, Low Ohmic Contacts, and Device Performance

(Invited) High κ/InGaAs for Ultimate CMOS – Interfacial Passivation, Low Ohmic Contacts, and Device Performance

EFFECTS OF A BARRIER LAYER IN INGAAS CHANNEL MOSFETS FOR ANALOG/ MIXED SIGNAL SYSTEM-ON-CHIP APPLICATIONS

Addition of a barrier layer in an InGaAs MOSFET, which shows promise for high performance logic applications due to enhanced electron mobility, further improves the electron mobility. We report, for the first time, a detailed investigation of the impact of different barrier layers on the analog performance of an InGaAs MOSFET. The device parameters for analog applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/IDS), drain conductance (gd), intrinsic gain, and unity-gain cutoff frequency (fT) are studied with the help of a device simulator. A barrier layer is found to improve the analog performance of such a device in general; with a double-barrier layer showing the best performance.

A Novel Digital Etch Technique for Deeply Scaled III-V MOSFETs

We demonstrate a new digital etch technique for controllably thinning III-V semiconductor heterostructures with sub-1-nm resolution. This is a two-step process consisting of low-power O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma oxidation, followed by diluted H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> SO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> rinse for selective oxide removal. This approach can etch a combination of InP, InGaAs, and InAlAs in a precise and nonselective manner. We have also developed a method to determine the etch rate per cycle, and to control the etch depth in actual device structures. For InP, the etch rate is ~0.9 nm/cycle. We illustrate the new process by fabricating L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> =60-nm self-aligned buried-channel InGaAs MOSFETs. These devices feature a composite gate dielectric consisting of 1-nm InP and 2-nm HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> for an overall sub-1-nm effective oxide thickness. A typical device shows a peak transconductance of 1.53 mS/μm(V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> =0.5 V), subthreshold swing of 89 mV/decade, and 102 mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> =0.05 and 0.5 V, respectively, and on current of 326 μA/μm at I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> =100 nA/μm and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> =0.5 V.

RF and DC Analysis of Stressed InGaAs MOSFETs

A complete reliability study of the DC and RF characteristics for InGaAs nMOSFETs with Al2O3/HfO2 dielectric is presented. The main stress variation at high frequencies is related to a threshold voltage shift, whereas no decrease is found in the maximum of the cutoff frequency and RF transconductance. Constant gate stress leads to a charge build up causing a threshold voltage shift. Furthermore, electron trapping at the drain side degrades the performance after hot carrier stress. The maximum DC transconductance is reduced following constant gate bias stress, by an increase in charge trapping at border defects. These border defects at the channel/high-κ interface are filled by cold carrier trapping when the transistor is turned on, whereas they do not respond at high frequencies.

Channel thickness dependence on InGaAs MOSFET with n-InP source for high current density

Channel thickness dependence on InGaAs MOSFET with n-InP source for high current density

Delay Time Component of InGaAs MOSFET Caused by Dynamic Source Resistance

Delay Time Component of InGaAs MOSFET Caused by Dynamic Source Resistance

Reliability of High-Mobility InGaAs Channel n-MOSFETs Under BTI Stress

The reliability performance of InxGa1-xAs n-MOSFETs with Al2O3 gate dielectric under positive-bias temperature instability stress is investigated. The following new phenomena are demonstrated: 1) There are high densities of fast interface traps Nit and slow oxide border traps NSOX near the interface between InGaAs and Al2O3. The border traps are more fragile under stress, and therefore, the stress mainly induces border traps. 2) The stress-induced border traps consist of permanent acceptor traps and recoverable donor traps. Acceptor trap energy density ΔDSOXAcceptor(E) is mainly distributed above the conduction band edge Ec of InGaAs with a tail extending to the midgap, whereas donor trap energy density ΔDSOXDonor(E) has a large distribution inside the InGaAs energy gap with a tail extending to the conduction band. 3) Flicker noise variation after stress and its correlation to the acceptor and donor trap generation and recovery are demonstrated. 4) The recoverable donor traps induce the subthreshold slope and off-current degradation in the stress phase and recover in the recovery phase and also induce continuous degradation of on-current in the recovery phase. The permanent acceptor traps induce the transconductance and on-current degradation. The long-term device lifetime is mainly determined by the generation rate of the acceptor traps. 5) Comprehensive comparison between the Si and InGaAs MOSFETs' degradation behaviors under bias temperature instability stress is presented. The physical recovery of donor oxide traps in dielectric in InGaAs/Al2O3 has never been observed in a Si MOS structure, deserving special attention and further investigation.

Performance and Variability Studies of InGaAs Gate-all-Around Nanowire MOSFETs

Furthering Si CMOS scaling requires development of high-mobility channel materials and advanced device structures to improve the electrostatic control. We demonstrate the fabrication of gate-all-around (GAA) indium gallium arsenide (InGaAs) MOSFETs with highly scaled atomic-layer-deposited gate dielectrics. InGaAs, with its high electron mobility, allows higher drive currents and other on-state performance compared to silicon. The GAA structure provides superior electrostatic control of the MOSFET channel with outstanding off-state performance. A subthreshold slope of 72 mV/dec, electron mobility of 764 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s, and an on-current of 1.59 mA/μm are demonstrated, for example. Variability studies on on-state and off-state performances caused by the number of nanowire channels are also presented.

Low interface defect density of atomic layer deposition BeO with self-cleaning reaction for InGaAs metal oxide semiconductor field effect transistors

In this paper, we discuss atomic configuration of atomic layer deposition (ALD) beryllium oxide (BeO) using the quantum chemistry to understand the theoretical origin. BeO has shorter bond length, higher reaction enthalpy, and larger bandgap energy compared with those of ALD aluminum oxide. It is shown that the excellent material properties of ALD BeO can reduce interface defect density due to the self-cleaning reaction and this contributes to the improvement of device performance of InGaAs MOSFETs. The low interface defect density and low leakage current of InGaAs MOSFET were demonstrated using X-ray photoelectron spectroscopy and the corresponding electrical results.

High-Performance InAs-On-Insulator n-MOSFETs With Ni-InGaAs S/D Realized by Contact Resistance Reduction Technology

We have systematically analyzed the components of source/drain (S/D) resistance (RSD) in InGaAs n-MOSFETs with Ni-InGaAs metal S/D. It is found that Ni-InGaAs has a low resistivity of ~250 μΩ·cm in a thickness of Ni-InGaAs (TNi-InGaAs) of down to ~4 nm. Contact resistance between the contact pads and Ni-InGaAs (RC) is found to be the most dominant component of RSD in control InGaAs MOSFETs, because of the existence of Ni oxides. By developing a surface cleaning process using NH4OH and H2 plasma for Ni-InGaAs surfaces, we have reduced RC down to 11 Ω·μm without any accompanying drawbacks. Also, the increase in the channel indium (In) content has provided further RSD reduction. Employing these RSD reduction technologies, we present 20-nm-channel length (Lch) InAs-on-insulator n-MOSFETs on Si substrates with Ni-InGaAs metal S/D. The devices provide a high maximum ON-current (ION) and maximum transconductance (Gm) of 2.38 mA/μm and 1.95 mS/μm at drain voltage (VD) of 0.5 V. This high performance is attributable to the low RSD realized by the surface cleaning process of Ni-InGaAs surfaces before the contact pad formation as well as the increase in the In content in the channel layer. Furthermore, it is found that the interface resistance (Rinterface) between Ni-InGaAs and InGaAs channels can be reduced down to 50 Ω·μm by increasing the In content in the channel layers.

Limiting Factors of Channel Mobility in III-V/Ge MOSFETs

MOSFETs using III-V/Ge channels have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. However, fundamental device physics on electrical properties of III-V/Ge MOSFETs such as mobility has not been fully clarified yet. In this paper, we address key issues for enhancing channel mobility in InGaAs/Ge MOSFETs. We have confirmed in Ge p-MOSFETs with ultrathin GeOx interfacial layers formed by plasma post oxidation that the GeOx thickness can control the peak mobility in a low Ns region. This fact is attributed to lower Dit near Ev, estimated from the S factor, in thicker GeOx. The relation between the peak mobility and the interface formation technologies is addressed. As for InGaAs nMOSFETs, we point out that the trapping of free electrons into interface states or slow states within the conduction band also significantly lowers electron mobility in InGaAs MOSFETs. As another critical factor for the electron mobility reduction, the influence of the body thickness on channel mobility is introduced. The thickness fluctuation scattering can be worse for III-V MOSFETs with lower effective mass and wider inversion-layer thickness. Thus, we have proposed MOS interface buffer channel structure, where InGaAs buffer layers sandwich InGaAs channels with higher In content. Actually, we have observed the significant mobility enhancement in the In0 .3Ga0 .7As/In0 .7Ga0 .3As/ In0 .3Ga0 .7As-OI structure over single In0 .7Ga0 .3As-OI structures.

Impact of Different Barrier Layers and Indium Content of the Channel on the Analog Performance of InGaAs MOSFETs

A barrier layer in an InGaAs MOSFET, which shows promise for high-performance logic applications due to enhanced electron mobility, is known to further improve the electron mobility. In this paper, a detailed investigation of the impact of different barrier layers on the analog performance of an InGaAs MOSFET is reported for the first time. The device parameters for analog applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/IDS), drain conductance (gd), intrinsic gain (gm/gd), and unity-gain cutoff frequency (fT) are studied with the help of a device simulator. A barrier layer is found to improve the analog performance of such a device in general; with a double-barrier layer showing the best performance. An investigation on the impact of varying the indium content in the channel on the analog performance of an InGaAs MOSFET with a double-barrier layer is also reported in this paper. It is found that a higher In content results in better analog performance of such devices.

Development of AlAsSb as a barrier material for ultra-thin-channel InGaAs nMOSFETs

ABSTRACTWe investigated AlAs0.56Sb0.44 epitaxial layers lattice-matched to InP grown by molecular beam epitaxy (MBE). Silicon (Si) and tellurium (Te) were studied as n-type dopants in AlAs0.56Sb0.44 material. Similar to most Sb-based materials, AlAs0.56Sb0.44 demonstrates a maximum active carrier concentration around low-1018 cm-3 when using Te as a dopant. We propose the use of a heavily Si-doped InAlAs layer embedded in the AlAsSb barrier as a modulation-doped layer. The In0.53Ga0.47As/AlAs0.56Sb0.44 double heterostructures with a 10 nm InGaAs well show an electron mobility of about 9400 cm2/V・s at 295 K and 32000 cm2/V・s at 46 K. A thinner 5 nm InGaAs well has an electron mobility of about 4300 cm2/V・s at 295 K. This study demonstrates that AlAs0.56Sb0.44 is a promising barrier material for highly scaled InGaAs MOSFETs and HEMTs.

On the Enhancement of the Drain Current in Indium-Rich InGaAs Surface-Channel MOSFETs

The effects of interface-trap states (Dit) and the shift of the charge neutrality level (CNL) on the enhancement of the drain current in In-rich surface-channel enhancement-mode n-type InGaAs MOSFETs are investigated. In addition to the increase in the bulk mobility, the shift of the CNL toward the conduction band together with high densities of Dit is responsible for the experimentally observed remarkable enhancement of the on-state drain current with increasing In content in the channel. However, when Dit is low, current enhancement is weak, and the location of the CNL has little effect on the current enhancement. Acceptor-type interface-trap states above the conduction-band minima (CBM) play an important role in determining the inversion-layer electron mobility. Representing Dit distribution above the CBM by a constant equal to the Dit value at the CNL causes an overestimation of the drain current at higher gate voltages. It is also observed that the extraction of Dit from the low-frequency gate C-V data is independent of the location of the CNL. We further show that the subthreshold slope (SS) is doubled due to Dit. However, the location of the CNL or the magnitude of Dit above the CBM has little effect on the SS.

Sub-100nm Non-Planar 3D InGaAs MOSFETs: Fabrication and Characterization

InGaAs MOSFETs have been considered promising candidate for post-Si logic devices beyond 14nm technology node. To meet the increasing demand in electrostatic control at sub-100nm channel lengths, non-planar 3D structures have been introduced to the fabrication of InGaAs MOSFETs. In this paper, the fabrication and characterization of various non-planar 3D InGaAs MOSFETs have been demonstrated and summarized, including InGaAs heterostructure FinFETs, InGaAs-on-nothing nanowire MOSFETs, and InGaAs gate-all-around nanowire MOSFETs. It is shown that the implementation of 3D structure greatly reduces short channel effect and improves scalability of InGaAs MOSFETs. The gate-all-around nanowire structure has been fabricated by a novel top-down approach for the first time and is found to offer great scalability down to at least 50nm channel length with good transport property, making InGaAs gate-all-around nanowire MOSFETs strong candidate for ultimately scaled III-V logic technology.