Limiting Factors of Channel Mobility in III-V/Ge MOSFETs

Abstract

MOSFETs using III-V/Ge channels have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. However, fundamental device physics on electrical properties of III-V/Ge MOSFETs such as mobility has not been fully clarified yet. In this paper, we address key issues for enhancing channel mobility in InGaAs/Ge MOSFETs. We have confirmed in Ge p-MOSFETs with ultrathin GeOx interfacial layers formed by plasma post oxidation that the GeOx thickness can control the peak mobility in a low Ns region. This fact is attributed to lower Dit near Ev, estimated from the S factor, in thicker GeOx. The relation between the peak mobility and the interface formation technologies is addressed. As for InGaAs nMOSFETs, we point out that the trapping of free electrons into interface states or slow states within the conduction band also significantly lowers electron mobility in InGaAs MOSFETs. As another critical factor for the electron mobility reduction, the influence of the body thickness on channel mobility is introduced. The thickness fluctuation scattering can be worse for III-V MOSFETs with lower effective mass and wider inversion-layer thickness. Thus, we have proposed MOS interface buffer channel structure, where InGaAs buffer layers sandwich InGaAs channels with higher In content. Actually, we have observed the significant mobility enhancement in the In0 .3Ga0 .7As/In0 .7Ga0 .3As/ In0 .3Ga0 .7As-OI structure over single In0 .7Ga0 .3As-OI structures.