A Novel Digital Etch Technique for Deeply Scaled III-V MOSFETs

Abstract

We demonstrate a new digital etch technique for controllably thinning III-V semiconductor heterostructures with sub-1-nm resolution. This is a two-step process consisting of low-power O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma oxidation, followed by diluted H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> SO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> rinse for selective oxide removal. This approach can etch a combination of InP, InGaAs, and InAlAs in a precise and nonselective manner. We have also developed a method to determine the etch rate per cycle, and to control the etch depth in actual device structures. For InP, the etch rate is ~0.9 nm/cycle. We illustrate the new process by fabricating L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> =60-nm self-aligned buried-channel InGaAs MOSFETs. These devices feature a composite gate dielectric consisting of 1-nm InP and 2-nm HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> for an overall sub-1-nm effective oxide thickness. A typical device shows a peak transconductance of 1.53 mS/μm(V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> =0.5 V), subthreshold swing of 89 mV/decade, and 102 mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> =0.05 and 0.5 V, respectively, and on current of 326 μA/μm at I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> =100 nA/μm and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> =0.5 V.