Sub-100nm Non-Planar 3D InGaAs MOSFETs: Fabrication and Characterization

Abstract

InGaAs MOSFETs have been considered promising candidate for post-Si logic devices beyond 14nm technology node. To meet the increasing demand in electrostatic control at sub-100nm channel lengths, non-planar 3D structures have been introduced to the fabrication of InGaAs MOSFETs. In this paper, the fabrication and characterization of various non-planar 3D InGaAs MOSFETs have been demonstrated and summarized, including InGaAs heterostructure FinFETs, InGaAs-on-nothing nanowire MOSFETs, and InGaAs gate-all-around nanowire MOSFETs. It is shown that the implementation of 3D structure greatly reduces short channel effect and improves scalability of InGaAs MOSFETs. The gate-all-around nanowire structure has been fabricated by a novel top-down approach for the first time and is found to offer great scalability down to at least 50nm channel length with good transport property, making InGaAs gate-all-around nanowire MOSFETs strong candidate for ultimately scaled III-V logic technology.