Independent-gate FinFET Research Articles

A look-up table-based processing-in-SRAM architecture for energy-efficient search applications

This paper presents an efficient in-memory computing architecture for search and logic function applications. The proposed design benefits from an SRAM cell, using two single-ended read bit-lines to enable binary and ternary content addressable memories (BCAM and TCAM) and logic functions. As our proposed cell benefits from Schmitt trigger inverters based on independent gate FinFETs. No data distraction occurs due to the half-selection issue. The results indicate no failure in the proposed method in the half-selected cells in the BCAM and TCAM functions. Moreover, the proposed cell shows 58% and 89% lower power in the write and read operations than the conventional SRAM-based IMC design. Also, by providing basic logic operations in the proposed design, applications with high-accuracy requirements can be implemented. Moreover, a neural network is also implemented to assess the proposed design in a practical application. The results show that our design consumes 41% and 50% lower energy than its counterparts.

10T FinFET based SRAM cell with improved stability for low power applications

ABSTRACT Due to scaling, many limitation arise for CMOS-based design memory cells in the nanometre regime, i.e. it becomes necessary to find a substitute for this design. Low power and high speed integrated circuits (ICs) are the demand of the electronics industry in many applications such as Internet of things (IoT) and electronics gadgets, e.g. Mobile, Laptops etc. Now, modern design ICs uses carbon nanotube FET or FinFET to design memory cells because of their excellent features of having low leakage and delay and improved performance. In this paper, two 10 transistor (10 T) FinFET design SRAM cells are proposed along with their hold, read, and write static noise margins (HSNM, RSNM, and WSNM), dynamic and static power consumption. These cells consume low power and provide high stability for electronic gadgets. In the proposed cells, we used a separate read and write path and back gate control method (BG). A comparative analysis of the proposed cells is done with the existing 10 T CMOS and FinFET based cells. All cells are simulated by using the tool HSPICE at 32 nm technology for a supply of 0.5 V. Cells 1 and 2 dissipate 69% and 85% less static power, 54% and 68% less read power and 17% and 56% less write power, respectively, compared to the 10 T FinFET cell. Results signify that the proposed independent gate (IG) FinFET based cells have the highest value of margins and the least value power consumption.

Analysis of IG FINFET based N-Bit Barrel Shifter

This paper presents a new energy efficient N-bit barrel shifter using IG FinFET in 20 nm technology. The independent gate based FinFET device having more attractive features than standard CMOS technology. The proposed N-bit barrel shifter using independent gate FINFET device reduces the low power consumption over MOSFET and simulation results are performed using H spice software. In this work, it is presented the electrical analysis in terms of signal delay propagation and energy consumption of compacted barrel circuit for shifting operation.

Stacking Techniquefor Low Power Sram

Static random access memory leakage current is becoming one of the critical issues for low-power systems. SRAM-based FinFET Double Gate has become a better option for profound submicron techniques owing to its better short channel effect. In this work, we review some of the leakage current sources and low power reduction technique to reduce leakage. As animprovement of our research work,6T SRAM memory cells can be implemented using independent gate FinFET which gives lower leakage as well as better performance over the shorted gate FinFET mode. This is also implemented using stacking technique to decrease leakage. Therefore, the power devoured by the different SRAM cells is likened with the Tanner tool in 45 nm technique.

The Optimizations of Dual-Threshold Independent-Gate FinFETs and Low-Power Circuit Designs

In this paper, a method of optimizing dual-threshold independent-gate FinFET devices is discussed, and the optimal circuit design is carried out by using these optimized devices. Dual-threshold independent-gate FinFETs include low threshold devices and high threshold devices. The low threshold device is equivalent to two merging parallel short-gate devices and high threshold device is equivalent to two merging series SG devices. We optimize the device mainly by selecting the appropriate gate work function, gate oxide thickness, silicon body thickness and so on. Our optimization is based on the Berkeley BSIMIMG model and verified by TCAD tool. Based on these optimized devices, we designed the compact basic logic gates and two new compact D-type flip-flops. Additionally, we developed a circuit synthesis method based on Binary Decision Diagram (BDD) and the optimized compact basic logic gates. Hspice simulations show that the circuits using the proposed dual-threshold IG FinFETs have better performance than the circuits directly using the short-gate devices.

An analytical model to assess DC characteristics of independent gate Si FinFETs

In this paper, Poisson's equation is utilized to find the potential distribution inside the channel of an independent gate FinFET device by adding the effect of channel height. The channel height of the device plays an important role in surface potential calculation when top gate voltage is applied. Using surface potential, an I - V model is developed, which can find the device current both in linear and saturation regions of operation. The model is tested on devices of different dimensions and good agreement between modeled and simulated results is observed, which validates the authenticity of the proposed model.

BDD-Based Topology Optimization for Low-Power DTIG FinFET Circuits

This paper proposed a logic synthesis method based on binary decision diagram (BDD) representation. The proposed method is optimized for dual-threshold independent-gate (DTIG) FinFET circuits. The algorithm of the BDD-based topology optimization is stated in detail. Some kinds of feature subgraph structures of a BDD are extracted by the extraction algorithm and then fed to mapping algorithm to get a final optimized circuit based on predefined DTIG FinFET logic gates. Some MCNC benchmark circuits are tested under the proposed synthesis method by comparing with ABC, DC tools. The simulations show that the proposed synthesis method can obtain performance improvement for DTIG FinFET circuits.

A low-leakage and high-writable SRAM cell with back-gate biasing in FinFET technology

This paper presents a novel low-leakage and high-writable 8T SRAM cell based on FinFET technology. This cell reduces leakage current and consequently leakage power by dynamically adjusting the back gate of the stacked independent-gate FinFET devices. Furthermore, these stacked transistors increase the write static noise margin of the proposed cell due to their role in reducing the strength of the pull-down network of the cross-coupled inverters. The characteristics of this cell are evaluated by device/circuit level simulations using Sentaurus device TCAD device simulator at different supply voltages and in the presence of process variations. The results indicate that the proposed SRAM cell reduces the static power by 37% and 56%, respectively, while providing comparable and even higher static noise margins, as compared to the 6T and 8T FinFET-based SRAM cells.

Design of FinFET Based Self-Biased OTA for Low Power Applications

This work explores the design of an Operational Trans conductance Amplifier (OTA) using Independent Gate (IG) FinFET. For the different configurations of FinFET such as IG, Low Power (LP) and Shorted Gate (SG), optimal gm and ro values have been found. FinFET devices are used to increase the performance by reducing the power dissipation as the front and back gate voltages are controlled independently. The designed three stage FinFET based OTA operates at 0.5 V power supply and achieves gain of 64 dB, 33 phase margin and 20 MHz unity gain frequency. The proposed OTA circuit is tested in Cadence virtuoso with FinFET 32nm BSIM-CMG model.

Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing

In this paper, we propose two independent gate (IG) FinFET SRAM cells that use PMOS access transistors and back-gate (BG) biasing to achieve a high-stability performance. In the first cell, the back-gate of the access transistors is connected to the adjacent storage nodes, and the back-gate of the pull-down transistors is dynamically biased. Simulations indicate that the first proposed cell offers higher read static noise-margin (SNM), higher write-ability, least static/dynamic power, and a comparable read current compared to the previous IG-6TSRAMs. The second cell is a novel independently-controlled-gate FinFET SRAM cell, which provides a high read stability, the highest write-ability, low static power dissipation and high read current compared to the previously reported independently-controlled-gate FinFET SchmitTrigger based SRAM cells. This cell supportsbit-interleaving property at VDD = 0.4 V with high read/write yields.

Comprehensive Optimization of Dual Threshold Independent-Gate FinFET and SRAM Cells

Independent-Gate (IG) FinFET is a promising device in circuit applications due to its two separated gates, which can be used independently. In this paper, we proposed a comprehensive method to optimize the Dual Threshold (DT) IG FinFET devices by carrying out modulations for the gate electrode work function, oxide thickness, and silicon body thickness. Titanium nitride (TiNx) is used as the tunable work function gate electrode for good performances. The thicknesses of the gate oxide and silicon body are swept by TCAD simulations to obtain the appropriate values. The verification simulation of the optimized transistors shows that the DT IG FinFETs can realize merging parallel and series transistors, respectively, and the current characteristics of the transistors are improved significantly. By extracting the BSIM-IMG model parameters, we can simulate the circuits composed of the proposed DT IG FinFET by using HSPICE with BSIM-IMG model. As practical examples, we optimized two novel 7T SRAM cells using DT IG FinFETs. HSPICE simulation results indicate that the new SRAM cells obtain higher write margin and read static noise margin with lower leakage power consumption than the other implementations.

Low power FinFET content addressable memory design for 5G communication networks

Content Addressable Memories (CAMs) are used in diverse applications, such as network protocols used in Wireless Sensor Networks (WSN), text analytics, reconfigurable computing and signal processing applications that require ultra-high speed and very low power consumption. In this work, a novel FinFET CAM using PMOS access transistors, based on PTM–MG transistor models in 22 nm and 14 nm technology is analyzed. Simulation results show that the Independent Gate (IG) FinFET CAM using PMOS access transistor exhibits a 38% improvement in the speed and 48% power consumption reduction compared to the shorted gate (SG) CAM based on 22 nm technology. Similarly, the proposed IG cell achieves a 5% improvement in speed and 50% reduction in power consumption when 14 nm technology is adopted. Hence the proposed IG cell in 14 nm has 6% improvement in speed and 59% less power consumption over 22 nm technology which is suitable for modern 5th generation communication networks.

Transistor Count Optimization in IG FinFET Network Design

Double-gate devices, like independent-gate (IG) FinFET, have introduced new possibilities and challenges in synthesis of transistor networks. Existing factorization methods and graph-based optimizations are not actually the most effective way to generate optimized IG FinFET based networks because only reducing the number of literals in a given Boolean expression does not guarantee the minimum transistor count. This paper presents two novel methods aiming the minimization of the number of devices in logic networks. The first contribution is a method for defactoring Boolean expressions able to apply the conventional factorization algorithms together with IG FinFET particularities, so improving it. The second contribution is a novel graph-based method that improves even more transistor arrangements by exploiting enhanced nonseries-parallel associations. Experimental results shown a significant reduction in the size of transistor networks delivered by the proposed methods.

Design of a low voltage low power self-biased OTA using independent gate FinFET and PTM models

In this paper a low power low voltage operational transconductance amplifier has been designed using IGFinFET. Pseudo differential pair and self-biased techniques have been used for rail-to-rail input operation of the OTA. The new technique used in this paper has the advantage of bulk-drive technique for low voltage analog designs without bulk-drive limitations. Using double gate FinFET, one gate has been used to adjust threshold voltage, while the input signal is applied to the other gate. Optimum gm and ro have been investigated for different gate configurations of the IGFinFET. Power consumption of the IGFinFET circuit is lower than its CMOS counterpart and shows good merits for analog design in analog and mixed signal applications. DFC method has been used for frequency compensation that needs smaller capacitors. Predictive Technology Model (PTM) 20nm IGFinFET has been employed for HSPICE simulations. The designed amplifier has 39.27dB gain with 45.05° phase margin and unity-gain bandwidth of 8.26MHz with 37.75μW power dissipation from a single 0.5V power supply.

Design of Ternary Content-Addressable Memories with Dynamically Power-gated Storage Cells Using FinFETs

An independent-gate FinFET can operate in two modes: SG (shorted-gate) and IG (independent-gate) modes, and thus a FinFET-based circuit offers rich design options for lower power, better performance or reduced transistor count. In this paper, we present two novel dynamically power-gated FinFET TCAM cells, called DPG-17T and DPG-16T, which power-gate the prefix data storage unit when storing a ‘don't care’ value. With the dynamic power-gating mechanism, DPG 17T/DPG-16T achieve lower power dissipation by eliminating the switching power of the comparison FinFETs and suppressing the leakage power of the prefix data storage when storing a ‘don't care’ value. Moreover, the discharge path of the matchline in DPG-17T/DPG-16T can be constructed with only one FinFET instead of two FinFETs, greatly boosting the search speed. Simulation results have shown that a TCAM of 64-word×128-bit using DPG-17T/DPG-16T can reduce the worst-case search delay by 53.0%/53.6% and improve the energy-delay product by 68.5%/70.4% when operating under a search rate of 4.0 GHz.

Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs

Recently, multigate field-effect transistors have started replacing traditional planar MOSFETs to keep pace with Moore’s Law in deep submicron technology. Among different multigate transistors, FinFETs have become the preferred choice of the semiconductor industry owing to low fabrication cost, superior performance, lower leakage, and design flexibility. The back and front gates of a FinFET can either be shorted or remain independent, leading to two modes of operation: Shorted-Gate (SG) and Independent-Gate (IG). For a given mode of operation, the physical parameters of the FinFET can either be symmetric or asymmetric in nature. In this article, for the first time, we analyze multiparameter asymmetric SG FinFETs and illustrate their potential for implementing logic gates and circuits that are both ultra-low-leakage and high-performance simultaneously. We restrict this work to SG devices because IG FinFETs (symmetric/asymmetric) suffer from severely degraded on-current, which makes them unattractive for high-performance designs. We first compare head-to-head all viable single- and multiparameter symmetric/asymmetric SG FinFETs. Among all such FinFETs, the traditional SG (which are symmetric in nature), Asymmetric Workfunction Shorted-Gate (AWSG), and Asymmetric Workfunction-Underlap Shorted-Gate (AWUSG) FinFETs show the most promise. We characterize these devices under process variations in gate length ( L G ), fin thickness ( T SI ), gate-oxide thickness ( T OX ), gate underlap ( L UN ), and gate-workfunction (Φ G ) as well as supply voltage ( V DD ) variations, followed by a gate-level leakage/delay analysis at different temperatures. Although AWSG FinFETs consume very low leakage power, they do suffer from performance degradation relative to SG FinFETs. Similarly, our study reveals that no other single-parameter asymmetric FinFET provides a good combination of low-power and high-performance design. We show that gates/circuits based on AWUSG FinFETs are faster, yet consume much less leakage power and less area than gates/circuits based on traditional SG FinFETs. We observe 53.4% (30.2%) maximum (average) reduction in total power at temperature T = 348 K while meeting the same delay constraint, with 14.2% (13.5%) reduction in area for AWUSG circuits relative to SG circuits. At T = 373 K , we see 68.6% (46.9%) maximum (average) reduction in total power.

Ultralow-power high-speed flip-flop based on multimode FinFETs

In this paper, we first reconstruct a novel planar static contention-free single-phase-clocked flipflop (S2CFF) based on high-performance fin-type field-effect transistors (FinFETs) to achieve high speed and ultralow power consumption. Benefiting from better control of the conductive channel, the shorted-gate (SG-mode) FinFET flip-flop obtains a persistent reduction of 56.7% in average power consumption as well as a considerable improvement in timing performance at a typical 10% data switching activity, while the low-power (LP-mode) FinFET flip-flop promotes the power reduction to 61.8% without appreciable degradation in speed. However, through further analysis of the simulation results, we have revealed an unnecessary energy loss caused by the redundant leaps of internal nodes at the static input ‘0’, which has a noticeable negative impact on total power consumption at low data switching activity. In order to overcome this defect, a conditional precharge technique is introduced to control the charging path, and we demonstrate that the independent-gate (IG-mode) FinFET is the best option for the added control transistor. The verification results indicate that our optimization reduces the power consumption by more than 50% at low data switching activity with an acceptable area and setup time penalty compared with that of LP-mode FinFET flip-flop.

Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design

Wide fan-in dynamic logic OR gate has always been an integral part of high speed microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always an issue of concern. For maintaining high noise immunity, various large sized PMOS keeper-based dynamic OR gates are proposed in the literature. These designs allow large leakage through them for maintaining high noise immunity which unnecessarily increases the power dissipation. This can be a critical issue for microprocessors used in battery operated devices. Independent gate (IG) FinFET devices are known to reduce leakage current through them using back gate biasing technique. In this paper, a novel FinFET-based wide fan-in dynamic OR gate has been proposed with effective leakage control and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining up to 90% higher noise immunity as compared to standard dynamic OR gate at low keeper size. This work also mathematically illustrates the effective leakage reduction capability of FinFET as compared to CMOS and hence proves its preference over CMOS in wide fan-in dynamic OR gate.

Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology

Among different multi-gate transistors, FinFETs and Trigate FETs have set themselves apart as the most promising candidates for the upcoming 22nm technology node and beyond owing to their superior device performance, lower leakage power consumption, and cost-effective fabrication process. Innovative circuit design and optimization techniques will be required to harness the power of multi-gate transistors, which in turn will depend on accurate leakage and timing characterization of these devices under spatial and environmental variations. Hence, in order to aid circuit designers, we present accurate analytical models using central composite rotatable design (CCRD) based on response surface methodology (RSM) to estimate the leakage current and delay of FinFET standard cells under the effect of variations in gate length ( L G ), fin thickness ( T SI ), gate-oxide thickness (T OX ), gate-workfunction (Φ G ), supply voltage ( V DD ), and temperature ( T ). To the best of our knowledge, this is the first such attempt to develop analytical models for leakage/delay estimation of FinFET logic gates. To derive these models, we employ TCAD device simulations of adjusted 2D device cross sections that have been shown to track TCAD device simulations of 3D device behavior within a 1--3% error range. This drastically reduces the CPU time of our modeling technique (by several orders of magnitude) without much loss in accuracy. We present analytical leakage and delay models for different sizes and logic styles (e.g., shorted-gate (SG) and independent-gate (IG) FinFETs at the 22nm technology node). Both leakage and delay estimates derived from the analytical models are in close agreement with quasi-Monte Carlo (QMC) simulation results (QMC simulations track the accuracy of Monte Carlo simulations, but are several orders of magnitude faster) obtained for different adjusted-2D logic gates with a root mean square error (RMSE) in the 0.23%--5.87% range.

Tri-Mode Independent Gate FinFET-Based SRAM With Pass-Gate Feedback: Technology–Circuit Co-Design for Enhanced Cell Stability

We present 6T SRAMs with pass-gate feedback using tri-mode independent gate (TMIG) FinFETs as the access transistors. We perform a comprehensive analysis of TMIG FinFETs and the proposed SRAM cell using our simulation framework, which is based on the non-equilibrium Green's function models for FinFETs. We compare our technique with the tied gate (TG) FinFET SRAM and the previously proposed independent gate (IG) FinFET SRAM with pass-gate feedback. The effects of quantum confinement in scaled FinFETs on the device and SRAM characteristics are analyzed in detail. We show that quantum confinement effects lead to severe degradation in access time and write-ability of the IG FinFET SRAM. On the other hand, the SRAM cell proposed in this paper shows 14% improvement in write-ability over the TG FinFET SRAM with comparable read stability, achieving mitigation of the read-write conflict. At the same time, 30% reduction in standby leakage and comparable hold stability is achieved at no cell area penalty, with only 14% increase in the cell access time. We also show that the array-level issues associated with pass-gate feedback are mitigated using the co-design technique presented in this paper.