Stacking Techniquefor Low Power Sram

Abstract

Static random access memory leakage current is becoming one of the critical issues for low-power systems. SRAM-based FinFET Double Gate has become a better option for profound submicron techniques owing to its better short channel effect. In this work, we review some of the leakage current sources and low power reduction technique to reduce leakage. As animprovement of our research work,6T SRAM memory cells can be implemented using independent gate FinFET which gives lower leakage as well as better performance over the shorted gate FinFET mode. This is also implemented using stacking technique to decrease leakage. Therefore, the power devoured by the different SRAM cells is likened with the Tanner tool in 45 nm technique.