A look-up table-based processing-in-SRAM architecture for energy-efficient search applications

Abstract

This paper presents an efficient in-memory computing architecture for search and logic function applications. The proposed design benefits from an SRAM cell, using two single-ended read bit-lines to enable binary and ternary content addressable memories (BCAM and TCAM) and logic functions. As our proposed cell benefits from Schmitt trigger inverters based on independent gate FinFETs. No data distraction occurs due to the half-selection issue. The results indicate no failure in the proposed method in the half-selected cells in the BCAM and TCAM functions. Moreover, the proposed cell shows 58% and 89% lower power in the write and read operations than the conventional SRAM-based IMC design. Also, by providing basic logic operations in the proposed design, applications with high-accuracy requirements can be implemented. Moreover, a neural network is also implemented to assess the proposed design in a practical application. The results show that our design consumes 41% and 50% lower energy than its counterparts.