Memory Design and Verification of SRAM-based Energy Efficient Ternary Content Addressable Memory

Abstract

Over the recent years, Ternary Content Addressable Memory (TCAM) cells have been extensively used to store look-up tables in high-speed internet routers, owing to their low memory access time. The initial architectures of TCAM were based off typical 6-T SRAM cells, which exhibit high power consumption. This paved the way for the exploration of read de-coupled logic for multi-transistor SRAM, thus tackling the issue of high-power consumption. In this paper we propose two TCAM architectures which show reduced power consumption when compared to typical TCAM architectures. TCAM circuits can be built using SRAM cells with additional circuitry. This approach has been followed in this paper. The proposed TCAM architectures incorporate the low power 6-T and 8-T SRAM cells into the circuit designs. The schematics of the TCAM cells were simulated and tested using Cadence Virtuoso using gpdk090 technology. The power consumption values and static noise margins (SNM) of the TCAM cells were obtained and analyzed. A 67% decrease in the cumulated power consumed for the low power (LP) 8-T-TCAM compared to the typical 8-T TCAM and a 17% reduction for the single-ended 6-T TCAM as compared to the typical 6-T TCAM, was noticed. This improved power, along with optimal SNM values for extreme temperatures, make them versatile for a wide variety of applications that require low power.