A non-volatile low-power TCAM design using racetrack memories

Abstract

This paper proposes a design of a Ternary Content Addressable Memory (TCAM) cell using racetrack memories (RMs) for non-volatile operation. Four RMs are utilized as storage elements and CMOS transistors are used as control elements for executing the write and search operations. The search operation of the TCAM cell utilizes novel circuits to read the RMs and compare data at cell and array levels. A simulation-based analysis shows that this cell has a high critical charge (so tolerant to a single event upset, SEU) and operates at a low CMOS feature size; the analysis is pursued at cell and array levels. A comparison with other non-volatile TCAM cells shows that the write/search delays and the read operating voltage of the proposed RM-based TCAM cell are superior to PCM (Phase Change Memory) and NAND Flash based TCAM cells.