10T FinFET based SRAM cell with improved stability for low power applications

Abstract

ABSTRACT Due to scaling, many limitation arise for CMOS-based design memory cells in the nanometre regime, i.e. it becomes necessary to find a substitute for this design. Low power and high speed integrated circuits (ICs) are the demand of the electronics industry in many applications such as Internet of things (IoT) and electronics gadgets, e.g. Mobile, Laptops etc. Now, modern design ICs uses carbon nanotube FET or FinFET to design memory cells because of their excellent features of having low leakage and delay and improved performance. In this paper, two 10 transistor (10 T) FinFET design SRAM cells are proposed along with their hold, read, and write static noise margins (HSNM, RSNM, and WSNM), dynamic and static power consumption. These cells consume low power and provide high stability for electronic gadgets. In the proposed cells, we used a separate read and write path and back gate control method (BG). A comparative analysis of the proposed cells is done with the existing 10 T CMOS and FinFET based cells. All cells are simulated by using the tool HSPICE at 32 nm technology for a supply of 0.5 V. Cells 1 and 2 dissipate 69% and 85% less static power, 54% and 68% less read power and 17% and 56% less write power, respectively, compared to the 10 T FinFET cell. Results signify that the proposed independent gate (IG) FinFET based cells have the highest value of margins and the least value power consumption.