In-memory Logic Research Articles

Al1−xScxSbyN1−y: An opportunity for ferroelectric semiconductor field effect transistor

For the in-memory computation architecture, a ferroelectric semiconductor field-effect transistor (FeSFET) incorporates ferroelectric material into the FET channel to realize logic and memory in a single device. The emerging group III nitride material Al1−xScxN provides an excellent platform to explore FeSFET, as this material has significant electric polarization, ferroelectric switching, and high carrier mobility. However, steps need to be taken to reduce the large band gap of ∼5 eV of Al1−xScxN to improve its transport property for in-memory logic applications. By state-of-the-art first principles analysis, here we predict that alloying a relatively small amount (less than ∼5%) of Sb impurities into Al1−xScxN very effectively reduces the band gap while maintaining excellent ferroelectricity. We show that the co-doped Sb and Sc act cooperatively to give a significant band bowing leading to a small band gap of ∼1.76 eV and a large polarization parameter ∼0.87 C/m2, in the quaternary Al1−xScxSbyN1−y compounds. The Sb impurity states become more continuous as a result of interactions with Sc and can be used for impurity-mediated transport. Based on the Landau-Khalatnikov model, the Landau parameters and the corresponding ferroelectric hysteresis loops are obtained for the quaternary compounds. These findings indicate that Al1−xScxSbyN1−y is an excellent candidate as the channel material of FeSFET.

Photoelectric In-Memory Logic and Computing Achieved in HfO2-Based Ferroelectric Optoelectronic Memcapacitors

Photoelectric In-Memory Logic and Computing Achieved in HfO₂-Based Ferroelectric Optoelectronic Memcapacitors

Multifunctional In-Memory Logics Based on a Dual-Gate Antiambipolar Transistor toward Non-von Neumann Computing Architecture.

In-memory computing may make it possible to realize non-von Neumann computing because the logic circuits are unified in the memory units. We investigated two types of in-memory logic operations, namely, two-input logic circuits and multifunctional artificial synapses. These were realized in a dual-gate antiambipolar transistor (AAT) with a ReS2/WSe2 heterojunction, in which polystyrene with a zinc phthalocyanine core (ZnPc-PS4) was incorporated as a memory layer. Here, reconfigurability is a key concept for both types of device operations and was achieved by merging the Λ-shaped transfer curve of the AAT and the nonvolatile memory effect of ZnPc-PS4. First, we achieved electrically reconfigurable two-input logic circuits. Versatile logic circuits such as AND, OR, NAND, NOR, and XOR circuits were demonstrated by taking advantage of the Λ-shaped transfer curve of the dual-gate AAT. Importantly, the nonvolatile memory function provided the electrical switching of the individual circuits between AND/OR, NAND/NOR, and XOR/NAND circuits with constant input signals. Second, the memory effect was applied to multifunctional artificial synapses. The inhibitory/excitatory and long-term potentiation/depression synaptic operations were electrically reconfigured simply by controlling one parameter (readout voltage), making three distinct responses possible even with the same presynaptic signals. These findings provide hints that may lead to the realization of new in-memory computing architectures beyond the current von Neumann computers.

Programmable Optoelectronic Synaptic Transistors Based on MoS2/Ta2NiS5 Heterojunction for Energy-Efficient Neuromorphic Optical Operation.

The optoelectronic synaptic transistors with various functions, broad spectral perception, and low power consumption are an urgent need for the development of advanced optical neural network systems. However, it remains a great challenge to realize the functional diversification of the systems on a single device. 2D van der Waals (vdW) materials can combine unique properties by stacking with each other to form heterojunctions, which may provide a strategy for solving this problem. Herein, an all-2D vdW heterojunction-based programmable optoelectronic synaptic transistor based on MoS2/Ta2NiS5 heterojunctions is demonstrated. The device implements reconfigurable, multilevel non-volatile memory (NVM) states through sequential modulation of multiple optical and electrical stimuli to achieve broadband (532-808nm), energy-efficient (17.2 fJ), hetero-synaptic functionality in a bionic manner. The intrinsic working mechanisms of the photogating effect caused by band alignment and the interfacial trapping defect modulation induced by gate voltage are revealed by Kelvin-probe force microscopy (KPFM) measurements and carrier transport analysis. Overall, the (opto)electronic synaptic weight controllability for combined in-sensor and in-memory logic processors is realized by the heterojunction properties. The proposed findings facilitate the technical realization of generic all 2D hetero-synapses for future artificial vision systems, opto-logical systems, and Internet of Things (IoT) entities.

Introducing Chiro-optical Activities in Photonic Synapses for Neuromorphic Computing and In-Memory Logic Operations.

In artificial synaptic devices aimed at mimicking neuromorphic computing systems, electrical or optical pulses, or both, are generally used as stimuli. In this work, we introduce chiral materials for tailoring the characteristics of photonic synaptic devices to achieve handedness-dependent neuromorphic computing and in-memory logic gates. In devices based on a pair of chiral perovskites, the use of circularly polarized light (CPL) as the optical stimuli mimicked a series of electrical and opto-synaptic functionalities in order to emulate the multifunctional complex behavior of the human brain. Upon illumination in this two-terminal device, anisotropy in current has been observed due to the out-of-plane carrier transport, originating from spin-selective carrier transport. More importantly, the logic gate achieved in devices based on optoelectronic memristors turned out to be chirality-dependent; while an R-device functioned as an AND gate, the device based on the same perovskite of the opposite chirality (S-device) acted as a NOR gate toward in-memory logic operations. These findings in chiral perovskite-based artificial synapses can identify further strategies for future neuromorphic computing, vision simulation, and artificial intelligence.

Coexistence of analog and digital memristive behaviors in MoO3 based devices for artificial synaptic and logic display applications

In-memory logic operations and neuromorphic computing inspired by the brain based on memristors are promising computing modes that can improve computational efficiency and avoid additional power consumption. However, implementing these two functions within the memristor same cell is often limited by the flexible conversion between digital and analog memristive behaviors. In this work, a memristive device with Ag/MoO3/Ti structure was developed using hydrothermal methods, which presents the evolution from capacitance-coupled memristive effect to self-rectifying non-zero crossing analog memristive behavior and then to digital memristive effect by adjusting the amplitude of applied voltage. Under low voltage region (Vamplitude ≤ 1.2 V), the non-zero crossing analog memristive effect with self-rectifying behavior is mainly attributed to the potential barrier at the interface and built-in electric field, while the digital memristive effect under high voltage region (Vamplitude ≥ 1.5 V) is mainly attributed to the formation and fracture of Ag conductive filaments (CFs). Moreover, the mechanism for the non-zero-crossing characteristic of device was proven by parallel connection of memristors and capacitors. Finally, the artificial synaptic and logic display functions were implemented using the as-prepared memristive unit. Therefore, this work provided guidance for understanding the non-zero-crossing memristive effect and the development of high-density multifunctional devices.

PANDA: Processing in Magnetic Random-Access Memory-Accelerated de Bruijn Graph-Based DNA Assembly

In this work, we present an efficient Processing in MRAM-Accelerated De Bruijn Graph-based DNA Assembly platform, named PANDA, based on an optimized and hardware-friendly genome assembly algorithm. PANDA is able to assemble large-scale DNA sequence datasets from all-pair overlaps. We first design a PANDA platform that exploits MRAM as computational memory and converts it to a potent processing unit for genome assembly. PANDA can not only execute efficient bulk bit-wise X(N)OR-based comparison/addition operations heavily required for the genome assembly task but also a full set of 2-/3-input logic operations inside the MRAM chip. We then develop a highly parallel and step-by-step hardware-friendly DNA assembly algorithm for PANDA that only requires the developed in-memory logic operations. The platform is then configured with a novel data partitioning and mapping technique that provides local storage and processing to utilize the algorithm level’s parallelism fully. The cross-layer simulation results demonstrate that PANDA reduces the run time and power by a factor of 18 and 11, respectively, compared with CPU. Moreover, speed-ups of up to 2.5 to 10× can be obtained over other recent processing in-memory platforms to perform the same task, like STT-MRAM, ReRAM, and DRAM.

Magnetic-ferroelectric synergic control of multilevel conducting states in van der Waals multiferroic tunnel junctions towards in-memory computing.

van der Waals (vdW) multiferroic tunnel junctions (MFTJs) based on two-dimensional materials have gained significant interest due to their potential applications in next-generation data storage and in-memory computing devices. In this study, we construct vdW MFTJs by employing monolayer Mn2Se3 as the spin-filter tunnel barrier, TiTe2 as the electrodes and In2S3 as the tunnel barrier to investigate the spin transport properties based on first-principles quantum transport calculations. It is highlighted that apparent tunneling magnetoresistance (TMR) and tunneling electroresistance (TER) effects with a maximum TMR ratio of 6237% and TER ratio of 1771% can be realized by using bilayer In2S3 as the tunnel barrier under finite bias. Furthermore, the physical origin of the distinguished TMR and TER effects is unraveled from the k||-resolved transmission spectra and spin-dependent projected local density of states analysis. Interestingly, four distinguishable conductance states reveal the implementation of four-state nonvolatile data storage using one MFTJ unit. More importantly, in-memory logic computing and multilevel data storage can be achieved at the same time by magnetic switching and electrical control, respectively. These results shed light on vdW MFTJs in the applications of in-memory computing as well as multilevel data storage devices.

A Flexible and Reliable RRAM-Based In-Memory Computing Architecture for Data-Intensive Applications

This paper proposes a practical, flexible, and reliable in-memory computing architecture for resistive-memory-based logic designs. Our design uses a new RRAM-based polymorphic in-memory logic gate implementing all 2-input Boolean logic functions to handle real-time applications like search engines. This design reduces the proposed architecture's power-delay product (PDP) compared to competing designs by utilizing the features of the RRAM device and the proposed reconfigurable sensing amplifier. Additionally, the simulation results on the ISCAS-89 and ITC-99 benchmarks at the 7nm technology node show that the suggested architecture's PDP is lower than the comparable state-of-the-art designs. A novel sense amplifier supporting all Boolean logic functions is also proposed to handle the applications with resistive-resistive-based inputs, such as search applications. After retrieving data from the main memory, the suggested sense amplifier computes the desired output. To assess the functionality of the suggested design in the presence of process variations, Monte Carlo simulations are conducted to authenticate the robustness and high-performance operation of the proposed design in different classes of resistive-memory-based logic in the presence of process variations. Our results further demonstrate that, compared to its counterpart, the suggested strategy dramatically reduces the energy consumption of the median, Max, and Min filters in real-world applications.

MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM

Conventional computing architectures based on the von Neumann structure are suffering from the severe ‘memory wall’ issue due to the isolation and speed mismatch between memory and processor. As a promising solution, the concept of logic in-memory (LiM) has been proposed to effectively reduce the overhead of data migration and has been extensively studied in various memory technologies such as SRAM, DRAM, MRAM, ReRAM, etc. Among them, SOT-MRAM combines the advantages of non-volatility, low static power consumption, ultra-fast read/write speed, and high density, has emerged as one of the most promising candidates for low-power LiM implementations. In this paper, four in-memory logic operations, AND, OR, MAJ and full-addition (FA), are proposed based on the Unipolar Switching (US) SOT-MRAM devices. Incorporating the emerging switching behavior of SOT-MRAM, these operations can be performed with the basic memory access operations (read/write) with negligible modifying peripheral circuits. Meanwhile, by optimizing the operation steps, the performance degradation caused by the instability of SOT-MRAM device can be minimized in the proposed LiM architecture. Detailed simulation results show that the proposed design can reduce the latency (energy) of AND, OR operations at least by 71.2%, 74.4% (30.0%, 35.4%) compared with the existing SRAM and STT-MRAM designs. For MAJ and FA operations, the performance is improved by at least 34.7% and 44.8% compared to the existing design. The robustness of our design is demonstrated by the 100% pass of the 1000 samples Monte Carlo simulations for the sufficient switching current margin and the effectiveness of basic operations.

Impact of sneak paths on in-memory logic design in memristive crossbars

Abstract Resistive Random Access Memory (RRAM), also termed as memristors, is a non-volatile memory where information is stored in memory cells in the form of resistance. Due to its non-volatile resistive switching properties, memristors, in the form of crossbars, are used for storing information, neuromorpic computing, and logic synthesis. In spite of the wide range of applications, memristive crossbars suffer from a so-called sneak path problem which results in an erroneous reading of memristor’s state. Till date, no or very few logic synthesis approaches for in-memory computing have considered the sneak path problem during the realizations of Boolean functions. In other words, the effects of sneak paths on the Boolean function realizations in crossbars still remain an open problem. In this paper, we have addressed this issue. In particular, we study the impacts of function realizations in two memristive crossbar structures: Zero-Transistor-One-Resistor (0T1R) and One-Transistor-One-Resistor (1T1R) in the presence of sneak paths. Experimental analysis on IWLS and ISCAS-85 benchmarks shows that even in the presence of sneak paths, the 1T1R crossbar structures with multiple rows and columns are the most efficient as compared to the 1T1R structures with single row and multiple columns in terms of crossbar size and number of execution cycles.

A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-V DD Assist and Bitline Leakage Compensation

Compute SRAM (CSRAM) can be configured to execute efficient in-memory logic computation and search operations, which is made possible by the multirow activation scheme. Nevertheless, simultaneous multirow activation introduces notorious compute access disturbance in 6T-based CSRAM designs. Existing solutions aim to mitigate the disturbance issue via weakening the access transistor strength, clamping the sensed bitline voltage swing, or substituting with read-decoupled SRAM bitcell designs. However, these techniques all come with significant design overheads of performance degradation in computational read and write accesses and increased layout area. This article presents multiple circuit-level techniques for the design and optimization of a reliable and high-speed 6T-based CSRAM. First, we propose a novel dual-split- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{DD}}$</tex-math> </inline-formula> (DSV)-assisted scheme for mitigating the compute access disturbance in 6T SRAM and simultaneously improving the computational read access performance. Second, we propose a leakage-compensated asymmetrical differential sense amplifier (LCAD-SA) to further improve the compute access performance. Third, we propose a DSV-assisted columnwise write scheme for accelerating the write performance. The proposed 6T CSRAM was implemented in the 28-nm CMOS, achieving a 1.18-GHz peak operating frequency, which is a 2.36 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> throughput improvement compared with that of the state-of-the-art CSRAM designs.

Efficient Method for Error Detection and Correction in In‐Memory Computing Based on Reliable Ex‐Logic Gates

In‐memory computing using memristor‐based stateful logic reveals high efficiency in the computing paradigm where the memory and computation are colocated. Still, variations in the memristor induce reliability issues for practical applications. Previous error detection and correction modules in the inmemory logic gates can handle the errors but only account for nonswitching errors of the output memristor, while the highly probable switching error of the output memristor is neglected, reducing overall efficiency. Moreover, the module operations use other added stateful logic gates, which may add errors. Herein, modules to handle both nonswitching and switching error cases within the three average steps using reliable logic gates consisting of five memristors are proposed. Detecting both error cases allows logic gates to be still operated in the optimized region for high‐energy efficiency and stability. In addition, combining two different logic families of stateful and sequential logic gates provides the reliability of the stateful logic gates and a possible solution to the peripheral complexity of cascading sequential logic gates. Although detection and correction are demonstrated in NOR and NAND logic gates with the memristor model, the other logic gates can be applied with the same algorithm with the appropriate module‐enable signal and input‐checker bits.

Reconfigurable Logic Operation Scheme Based on Gate-Tunable CBRAM

The traditional von Neumann architecture features large transfer latency and power dissipation. In-memory computing has been widely investigated in an effort to negotiate this hurdle. Herein, gate-tunable conductive bridge random access memory (GCBRAM) is proposed to construct in-memory computing. GCBRAM has a flexible modulation dimension, which can reduce the sensitivity of the selection of compensation resistors. A reconfigurable logic circuit based on GCBRAM has been developed, and the quantity of compensation resistors has been reduced. A full adder based on a GCBRAM circuit has been demonstrated, and the number of compensation resistors has been minimized compared with previous results using basic logic gates. To the best of our knowledge, full adder based on GCBRAM (six GCBRAM, seven steps) is the most compact form developed to date. This work represents the realization of a new form of in-memory logic with lower hardware costs, which can facilitate the development of in-memory computing.

Combining negative photoconductivity and resistive switching towards in-memory logic operations.

A family of rudorffites based on silver-bismuth-iodide shows a transition from a conventional positive photoconductivity (PPC) to an unusual negative photoconductivity (NPC) upon variation in the precursor stoichiometry while forming the rudorffites. The NPC has arisen in silver-rich rudorffites due to the generation of illumination-induced trap-states which prompted the recombination of charge carriers and thereby a decrease in the conductivity of the compounds. In addition to photoconductivity, sandwiched devices based on all the rudorffites exhibited resistive switching between a pristine high resistive state (HRS) and a low resistive state (LRS) under a suitable voltage pulse; the switching process, which is reversible, is associated with a memory phenomenon. The devices based on NPC-exhibiting rudorffites switched to the HRS under illumination as well. That is, the resistive state of the devices could be controlled through both electrical and optical inputs. We employed such interesting optoelectronic properties of NPC-exhibiting rudorffites to exhibit OR logic gate operation. Because the devices could function as a logic gate and store the resistive state as well, we concluded that the materials could be an ideal candidate for in-memory logic operations.

AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device

Traditional CMOS-based von-Neumann computer architecture faces the issue of memory wall that the limitation of bus-bandwidth and the speed mismatch between processor and memory restrict the efficiency of data processing along with an irreducible energy consumption conducted by data movement, especially in some data-intensive applications. Recently, some novel in-memory computing (IMC) paradigms developed by utilizing the characteristics of different non-volatile memories provide promising ways to overcome the bottleneck of memory wall. Here, we propose a new IMC unit based on a memory array with the core element of magnetoelectric spin-orbit logic (MESO) device (AIMCU-MESO), in which the characteristics of the MESO device are exploited to achieve several in-memory logic operations with the functions of NAND, NOR, and XOR in the MESO-based memory array. With the aid of some transistor-based switches, these logic operations can be achieved between any two MESOs in the array. Furthermore, the computing process of a 1-bit full adder (FA) is achieved in AIMCU-MESO by the in-memory logic manner to demonstrate the ability of logic cascading. The result of SPICE simulation for achieving the 1-bit FA using MESO devices is demonstrated, and the performances are compared with other designs of spintronics-based devices. Compared to multilevel voltage-controlled spin-orbit torque–based magnetic memory, the proposed design demonstrates 71.4% and 49.2% reductions in terms of storage delay and logic delay, respectively.

Room-temperature logic-in-memory operations in single-metallofullerene devices.

In-memory computing provides an opportunity to meet the growing demands of large data-driven applications such as machine learning, by colocating logic operations and data storage. Despite being regarded as the ultimate solution for high-density integration and low-power manipulation, the use of spin or electric dipole at the single-molecule level to realize in-memory logic functions has yet to be realized at room temperature, due to their random orientation. Here, we demonstrate logic-in-memory operations, based on single electric dipole flipping in a two-terminal single-metallofullerene (Sc2C2@Cs(hept)-C88) device at room temperature. By applying a low voltage of ±0.8 V to the single-metallofullerene junction, we found that the digital information recorded among the different dipole states could be reversibly encoded in situ and stored. As a consequence, 14 types of Boolean logic operation were shown from a single-metallofullerene device. Density functional theory calculations reveal that the non-volatile memory behaviour comes from dipole reorientation of the [Sc2C2] group in the fullerene cage. This proof-of-concept represents a major step towards room-temperature electrically manipulated, low-power, two-terminal in-memory logic devices and a direction for in-memory computing using nanoelectronic devices.

Research Progress on Memristor: From Synapses to Computing Systems

As the limits of transistor technology are approached, feature size in integrated circuit transistors has been reduced very near to the minimum physically-realizable channel length, and it has become increasingly difficult to meet expectations outlined by Moore’s law. As one of the most promising devices to replace transistors, memristors have many excellent properties that can be leveraged to develop new types of neural and non-von Neumann computing systems, which are expected to revolutionize information-processing technology. This survey provides a comparative overview of research progress on memristors. Different memristor synaptic devices are classified according to stimulation patterns and the working mechanisms of these various synaptic devices are analyzed in detail. Crossbar-based memristors have demonstrated advantages in physically executing vector-matrix multiplication and enabling highly power-efficient and area-efficient neuromorphic system designs. The extensive uses of crossbar-based memristors cover in-memory logic, vector-matrix multiplication, and many other fundamental computing operations. Furthermore, memristor-based architectures for efficient neural network training and inference have been studied. However, memristors have non-ideal properties due to programming inaccuracies and device imperfections from fabrication, which lead to error or mismatch in computed results. To build reliable memristor-based designs, circuit-level, algorithm-level, and system-level solutions to memristor reliability issues are being studied. To this end, state-of-the-art realizations of memristor crossbars, crossbar-based designs, and peripheral circuitry are presented, which show both promising full-system inference accuracy and excellent power efficiency in multiple tasks. Memristor in-situ learning benefits from high energy efficiency and biologically-imitative characteristics, which are conducive to further realizing hardware acceleration of cognitive learning. At present, the learning and training processes of brain-like networks are complex, presenting great challenges for network design and implementation.

Reliable Domain‐Specific Exclusive Logic Gates Using Reconfigurable Sequential Logic Based on Antiparallel Bipolar Memristors

Domain-Specific In-Memory Logic Gates As the total amount of data in computation rapidly increases, in-memory logic gates gain great attraction to address the von-Neumann bottleneck problem. In article number 2100267, Cheol Seong Hwang and co-workers present a new type of in-memory logic gates with a low voltage-stress level to execute exclusive-OR logic operations. The proposed logic gates have high compatibility with other logic gates in a crossbar array, which is utilized to implement a full adder-subtractor and multiplier. [Correction added on May 26, 2022, after first online publication: the inside back cover image and description were changed.]

CryoCiM: Cryogenic compute-in-memory based on the quantum anomalous Hall effect

The scaling of the already matured complementary metal-oxide-semiconductor technology is steadily approaching its physical limit, motivating the quest for a suitable alternative. Cryogenic operation offers a promising pathway toward continued improvement in computing speed and energy efficiency without aggressive scaling. However, the memory wall bottleneck of the traditional von-Neumann architecture persists even at cryogenic temperature. That is where a compute-in-memory (CiM) architecture, which embeds computing within the memory unit, comes into play. Computations within the memory unit help to reduce the expensive data transfer between the memory and the computing units. Therefore, CiM provides extreme energy efficiency that can enable lower cooling cost at cryogenic temperature. In this work, we demonstrate CryoCiM, a cryogenic compute-in-memory framework utilizing a nonvolatile memory system based on the quantum anomalous Hall effect (QAHE). Our design can perform memory read/write and universal binary logic operations (NAND, NOR, and XOR). We custom design a peripheral circuit assembly that can perform the read/write and single-cycle in-memory logic operations. The utilization of a QAHE-based memory system promises robustness against process variations, through the usage of topologically protected resistive states for data storage. CryoCiM is a major step toward utilizing exclusively cryogenic phenomena to serve the dual purpose of storage and computation with ultra-low power (∼nano-watts) operations.