Reconfigurable Logic Operation Scheme Based on Gate-Tunable CBRAM

Abstract

The traditional von Neumann architecture features large transfer latency and power dissipation. In-memory computing has been widely investigated in an effort to negotiate this hurdle. Herein, gate-tunable conductive bridge random access memory (GCBRAM) is proposed to construct in-memory computing. GCBRAM has a flexible modulation dimension, which can reduce the sensitivity of the selection of compensation resistors. A reconfigurable logic circuit based on GCBRAM has been developed, and the quantity of compensation resistors has been reduced. A full adder based on a GCBRAM circuit has been demonstrated, and the number of compensation resistors has been minimized compared with previous results using basic logic gates. To the best of our knowledge, full adder based on GCBRAM (six GCBRAM, seven steps) is the most compact form developed to date. This work represents the realization of a new form of in-memory logic with lower hardware costs, which can facilitate the development of in-memory computing.