Abstract
Domain-Specific In-Memory Logic Gates As the total amount of data in computation rapidly increases, in-memory logic gates gain great attraction to address the von-Neumann bottleneck problem. In article number 2100267, Cheol Seong Hwang and co-workers present a new type of in-memory logic gates with a low voltage-stress level to execute exclusive-OR logic operations. The proposed logic gates have high compatibility with other logic gates in a crossbar array, which is utilized to implement a full adder-subtractor and multiplier. [Correction added on May 26, 2022, after first online publication: the inside back cover image and description were changed.]
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
