A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-V DD Assist and Bitline Leakage Compensation

Abstract

Compute SRAM (CSRAM) can be configured to execute efficient in-memory logic computation and search operations, which is made possible by the multirow activation scheme. Nevertheless, simultaneous multirow activation introduces notorious compute access disturbance in 6T-based CSRAM designs. Existing solutions aim to mitigate the disturbance issue via weakening the access transistor strength, clamping the sensed bitline voltage swing, or substituting with read-decoupled SRAM bitcell designs. However, these techniques all come with significant design overheads of performance degradation in computational read and write accesses and increased layout area. This article presents multiple circuit-level techniques for the design and optimization of a reliable and high-speed 6T-based CSRAM. First, we propose a novel dual-split- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text{DD}}$</tex-math> </inline-formula> (DSV)-assisted scheme for mitigating the compute access disturbance in 6T SRAM and simultaneously improving the computational read access performance. Second, we propose a leakage-compensated asymmetrical differential sense amplifier (LCAD-SA) to further improve the compute access performance. Third, we propose a DSV-assisted columnwise write scheme for accelerating the write performance. The proposed 6T CSRAM was implemented in the 28-nm CMOS, achieving a 1.18-GHz peak operating frequency, which is a 2.36 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> throughput improvement compared with that of the state-of-the-art CSRAM designs.