A 22-nm FDSOI 8T SRAM Based Time-Domain CIM for Energy-Efficient DNN Accelerators

Abstract

In memory computation for Deep neural networks (DNNs) applications is an attractive approach to improve the energy efficiency of MAC operations under a memory-wall constraint, since it is highly parallel and can save a great amount of computation and memory access power. In this paper, we propose a time-domain compute in memory (CIM) design based on Fully Depleted Silicon On Insulator (FD-SOI) 8T SRAM. A <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$128\mathrm{x}128$</tex> 8T SRAM bit-cell array is built for processing a vector-matrix multiplication (or parallel dot-products) with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8\mathrm{x}$</tex> binary (0 or 1) inputs, in-array 8-bits weights, and 8bits output precision for DNN applications. The column-wise TDC converts the delay accumulation results to 8bits output codes using replica bit-cells for each conversion. Monte-Carlo simulations have verified both linearity and process variation. The energy efficiency of the 8bits operation is 32.8TOPS/W at 8bits TDC mode using 0.9V supply and 20MHz.