Improvement In Noise Margin Research Articles

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

In this paper, a carbon nanotube field-effect transistor (CNTFET) based low power and robust ternary SRAM (TSRAM) cell with enhanced static noise margin (SNM) has been proposed. The proposed cell uses a low-power cell core and a stack of 2 CNTFETs to discharge the read bit line (RBL) to ground, unlike the previous SRAM designs which use read buffers or transmission gates (TG) to alter the voltage levels on the RBL. The proposed TSRAM cell has been simulated relentlessly, using the Stanford 32 nm CNTFET technology mode file with Synopsis HSPICE tool under various operating conditions. Unlike other designs, the cross-coupled ternary inverters used as the cell core in the proposed TSRAM show higher gain and steep curves in the transition region mitigating the static power of the cell. The simulation results exhibit improvements in performance parameters like power consumption, energy, noise margins, and reliability. At 0.9 V supply voltage, the proposed TSRAM cell offers 52.44% and 43.17% reduction in write and read static power, a PDP reduction of 35.29% in comparison, and a 36.36% improvement in SNM compared to the best designs under investigation. Also, the proposed TSRAM design shows higher robustness compared to other designs.

Design and reliability assessment of an ultra-thin body electrostatically doped bipolar transistor for mixed signal applications

Shrinking of the thickness of silicon on insulator (SOI) has been proposed as a potential solution for scaling down the physical base length of symmetric lateral electrostatically doped bipolar transistors. An ultra-thin body device that utilizes the full SOI thickness has been presented and the performance of the same is investigated in detail. The device features two distinct doping techniques: work function-induced electrostatic doping (WED) and bias-induced electrostatic doping (BED). The proposed design approach leads to significant improvements in gain and cut-off frequency compared to previously reported designs. The resulting devices exhibit peak current gain β values >1100, ft>500 GHz, fmax>1300 GHz. Moreover, these improved device performance matrices get translated into better performance of universal gates with low rise and fall time of ∼1.3 ns, and improved noise margin performance in static random access memory (SRAM) device of 0.43 and 0.41 for WED and BED based devices respectively. Furthermore, the study investigates the reliability of the device concerning breakdown voltage and its response to different temperature conditions. The findings reveal a decline in the β value for WED-based devices when subjected to temperatures exceeding 340 K. In contrast, BED-based devices demonstrate a comparatively smaller variation in β at temperatures above 340 K. These results show the potential of the proposed device for mixed-signal and digital circuit applications.

Monolithic n‐Type Metal–Oxide–Semiconductor Inverter Integrated Circuits Based on Wide and Ultrawide Bandgap Semiconductors

Wide bandgap (WBG) and ultrawide bandgap (UWBG) semiconductors in n‐type metal–oxide–semiconductor (n‐MOS) integrated circuits (ICs) are increasingly being explored for their potential applications in the rapidly developing field of electronics. This review comprehensively examines the role of n‐MOS inverters underpinned by WBG and UWBG semiconductors and their application possibilities. It delves into various n‐MOS inverter topologies, including resistive, enhancement or diode‐load, depletion‐load, and pseudo‐complementary MOS inverter topologies. Each topology's operational principles, unique advantages, and potential performance are elucidated in detail. Finally, these topologies are simulated using the Advanced Design System software for a fair comparison between various topologies. The literature and simulation results show that the pseudo‐D topology has the best gain and improved noise margin. The review methodology involves an extensive exploration of WBG/UWBG n‐MOS inverters to advance the current understanding of WBG/UWBG n‐MOS‐based ICs.

A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis

This study investigates the effects of temperature on RF/Analog and linearity parameters using a 3 nm technology node Step-Negative capacitance FinFET (SNC-FinFET) for the first time. The SNC-FinFET exhibits superior performance compared to the conventional step architecture, with an enhancement of 7.2% in ION (ON-current), 73.58% in IOFF (OFF-current), excellent SS (Sub-threshold Swing) of 57.51 mV/decade, and a barrier rising of 52.38%. This is due to prior DC analysis that led to the extraction of the electrical parameters such as ION, IOFF, SS and threshold voltage (VT). After that, dimensional analysis is being done in terms of gate length (LG), fin widths (Wfin1 and Wfin2), and fin heights (Hfin1 and Hfin2). The optimized dimensions for this study are LG = 18 nm, Wfin1 = 5 nm, Wfin2 = 3 nm, Hfin1 = 50 nm, and Hfin2 = 14 nm. From this point on, using the same SNC-FinFET with the optimized dimension, varying the temperature from 250 K to 400 K, degrades the RF/analog characteristics while exhibiting the opposite trend for linearity, with improvements of 40.36%, 67.42%, 49.59%, and 62.31% in the 2nd order harmonic, 3rd order harmonic, 2nd order Voltage Intercept Point, and 3rd order Voltage Intercept Point, respectively. The proposed device performance is also analyzed at the circuit level followed by noise margin calculation where at T = 400 K 46.36% of improvement in noise margin is encountered.

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

Junctionless FinFET devices are a substitute for conventional FinFET devices due to their short channel effects and easy manufacturing at sub 22 nm technology node. The manuscript presents an 8T-SRAM cell based on tri-gate junctionless FinFET technology. The FinFET device is designed with source/drain of Si material and the channel as a stack of Si − Si 0.75 Ge 0.25 − Si. The proposed SRAM cell structure consists of a CMOS inverter with stacked p-FinFETs, improving its performance in terms of noise margin and leakage power consumption. The manuscript investigates the variation of Static Noise Margin (SNM), leakage power dissipation and delay with supply voltage to analyze the sub-threshold operation of SRAM cell. The results reveal that the cascaded p-FinFETs minimize the leakage current owing to the stack effect, resulting in improved noise margin and lower leakage power. The stacked p-FinFET devices based SRAM cell achieves 1.11x read noise margin, 1.11x hold noise margin, −1.08x write noise margin and 57.1% less leakage power compared to conventional SRAM cell at 1.0 V. However, it exhibits more delay due to increased resistance and capacitance of the cascaded transistors. The process variation analysis is also performed to investigate the SNM distribution using monte-carlo simulation by taking 10,000 samples. The results indicate that the SRAM cell structures provide higher than 6σ yield at range of supply voltages.

A Single-Ended 9T SRAM Cell With Improved Noise Margin for Low-Power Applications Used in LEDoS

As a silicon-based microdisplay for Augment reality (AR), the high power dissipation of digital CMOS driver is a significant barrier to approaching the higher performance of microdisplay. In this paper, a new low-power SRAM cell with a single bitline is proposed to reduce the power dissipation of digital CMOS drivers. Compared with conventional differential 6T SRAM cell, the proposed 9T uses the single-ended read/write and read/write separation technology by reducing bitline and adding word lines, and write/read static noise margin (WSNM/RSNM) has been improved while the power dissipation is reduced effectively by stacking effect. When VDD is 0.8 V, the proposed cell achieves 1.4× and 2.2× improvement in WSNM and RSNM compared to D6T. Besides, the proposed cell consumes 1.4× less power during hold mode compared to D6T at VDD=0.8 V.

Experimental and Theoretical Evidence of Charge Injection Barrier Control by Small-Molecular Charge Injection Layer and Its Effects on Organic–Inorganic Complementary Inverters

Introducing a contact charge injection layer at the interface between the contact electrode and active materials is considered crucial to obtain efficient charge injection behaviors in thin-film transistors (TFTs). Here, we investigate the effect of a small molecule contact charge injection layer through experimental results and theoretical calculations. We found limited electrical characteristics derived from contact resistance in C8-BTBT TFTs with C8-BTBT as the channel and Au as the electrode. We experimentally demonstrated that the limited electrical characteristics of C8-BTBT TFT can be improved by inserting dinaphtho[2,3-b: <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{\prime} $ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3^{\prime} $ </tex-math></inline-formula> -f]thieno [3,2-b] thiophene (DNTT), which has a low contact resistance at the junction with Au, as a charge injection layer. The results of improved contact properties through the DNTT charge injection layer were also consistent with the results of energy structural simulations. Furthermore, we verified the effect of the DNTT charge injection layer at the circuit level through improved noise margin characteristics in the complementary inverter composed of asymmetric charge injection layer TFT (ACIL-TFT) and a-indium gallium zinc oxide (IGZO) TFT.

Systematically-optimized charge transport properties in cumulatively solution-coated zinc tin oxide and applications for complementary inverter circuits combining organic p-type transistors

Zinc-tin-oxide (ZTO) is considered as a promising alternative thin-film semiconductors due to its merits of Earth-abundant materials, non-toxicity, and solution-processable low-cost manufacturing. However, there is still insufficient effort to implement a ZTO-based practical applications such as integrated circuits due to the lack of desirable switching behavior for circuit operation. In this context, we systematically investigate a solution processed ZTO film through a comprehensive analysis including scanning electron microscopy (SEM), atomic force microscopy (AFM), transmission line method (TLM), and X-ray photoelectron spectroscopy (XPS). We also fabricate the synthesized ZTO-based transistors, and characteristics of the transistors are evaluated depending on annealing temperature and number of coatings. Through the systematic investigation, this study obtains the suitable turn-on voltage of V TO = 0.15 V as well as uniform charge transport property of 2.14 cm 2 /V∙s ± 5.14%. Furthermore, we apply the ZTO transistor optimized for the circuit to the complementary inverter logic, and the measured inverter circuit provides an excellent voltage gain of 141.18 V/V and improved noise margin as high as 71.4% of half the supply voltage. • ZTO films were characterized by scanning electron microscopy, atomic force microscopy, and X-ray photoelectron spectroscopy. • Thickness-dependent ZTO TFT characteristics were investigated. • Morphological and chemical composition variations by annealing temperature were studied. • A complementary inverter using ZTO, DNTT TFTs with a voltage gain of 141.18 V/V and a noise margin of 71.4% was demonstrated.

Power and Noise Reduction of High-Frequency Variable Gain Amplifier

This work illustrates the design of the cell-based variable-gain amplifier (VGA) with less power consumption and improved noise margin. The variable gain amplifier is incorporated into the current wireless front-end modules. The body-bias technique in the n channel MOSFET (n-MOS) devices greatly aided in the power reduction of the cells. The device characteristics were fine-tuned to get better gain and bandwidth and reduced the supply voltage. This technique ultimately reduced the number of cell stages required to meet the expectation. The reduction of the supply voltage and the technology upscaling helped to improve the noise margin. The presented unit cell achieved accurate dB-linear characteristics across a wide tuning range, based on a unique gain control method with a combination of sub-threshold n-MOS and saturation n-MOS transistors as active loads. A 7-cell reconfigurable VGA is simulated in 0.18-[Formula: see text]m Complementary MOSFET technology to verify the concept. The simulation results showed that the bandwidth of the VGA is greater than 2.5[Formula: see text]GHz, while less than 0.78[Formula: see text]mW is consumed from a 1.5-V supply. A noise figure of 23.7[Formula: see text]dB is measured. Also, the VGA achieves a gain control range of 19[Formula: see text]dB with a gain error less than [Formula: see text][Formula: see text]dB or 26.3%. These results make the designed amplifier adequate for high-frequency applications.

Effect of back gate biasing in negative capacitance field effect transistor

In this paper, we have studied the effect of back gate bias technique in negative capacitance field effect transistor. In N-NCFET, OFF current decreases and threshold voltage increases with positive back gate bias, while with negative back gate bias, OFF current increases and threshold voltage decreases. This behavior of back gate bias in N-NCFET is quite different as compared to N-MOSFET. The primary reason behind this contradictory behavior is the dependence of internal node voltage (VMOS) on the body terminal of N-NCFET via bulk coupling factor. Further, we have utilized this property to design NCFET based inverter.Various figure of merits like noise margin, delay, static power dissipation and dynamic power dissipation is studied for the designed inverter. The designed inverter with suggested back gate bias shows 16% and 13.9% improved noise margin, and reduced delay performance respectively as compared to conventional NCFET without bias. Also, the power dissipation parameter (static and dynamic) is reduced by 90.1% and 3.8% respectively. We have also seen the effect of channel length scaling in the NCFET, decrement in the channel length improves the gate stack capacitance of NCFET which leads to decrement in OFF current at lower technology node.

Control of Charge Transport Properties in Molybdenum Diselenide Field-Effect Transistors for Enhanced Noise-Margin and Inverter Characteristics

Ambipolar field-effect transistor (FET) capable of transporting both holes and electrons has the advantage of operating as both p-type and n-type with a single device depending on the voltage bias condition. Among transition metal dichalcogenides (TMDs), molybdenum diselenide (MoSe₂), which has ambipolar properties, exhibits n-type dominant electrical characteristics. As a result, a digital inverter implemented only using pristine MoSe₂ FETs exhibited asymmetric and limited output swing characteristics because of the difficulty in pull-up operation. Therefore, a method for improving the p-type characteristics of MoSe₂ is needed to implement a complementary metal&#x2013;oxide&#x2013;semiconductor (CMOS)-like digital inverter using only MoSe₂. In this study, an n-type dominant MoSe₂ FET was adjusted to have p-type dominant characteristics through annealing process. Raman spectroscopy was used to compare the transistor with previous studies. Statistical analysis showed that the charge transport behavior was reproduced in multiple devices. The p-type enhanced MoSe₂ FET was applied as a pull-up transistor of a digital inverter to present the practicality of the annealing process to improve the p-type characteristics of the MoSe₂ FET. Eventually, a more symmetrical output swing and improved noise margin were achieved compared to a digital inverter composed of only n-type dominant MoSe₂ FETs.

Half-Select Disturb-Free 10T Tunnel FET SRAM Cell With Improved Noise Margin and Low Power Consumption

Tunnel field-effect transistors (TFETs) have become a potential candidate for replacing traditional MOSFETs in ultralow-power applications, in future. However, the forward p-i-n current of the TFET can seriously deteriorate the performance of the static random-access memory (SRAM) circuit. This brief proposes a half-select disturb-free 10T TFET SRAM cell with cascode isolation transistors. The proposed 10T SRAM cell can avoid the forward p-i-n current, drastically decreasing its leakage power consumption. At a supply voltage of 0.6 V, the leakage power consumption of the proposed 10T TFET SRAM cell is approximately four orders of magnitude lower than those of the outward-facing access transistor 6T (O_6T)/7T and the Schmitt–Trigger 10T (ST_10T) SRAM cells; the write power consumption is approximately 97% and 98% lower than those of the O_6T/7T/ST_10T and the combinational access 10T (CA_10T) SRAM cells, respectively. Moreover, the 10T SRAM cell exhibits 20% and 57% higher read static noise margin(RSNM) than those of the O_6T/7T and ST_10T cells, 115% and 411% higher write static noise margin(WSNM) than those of O_6T/7T and CA_10T, respectively, 20% higher hold static noise(HSNM) than those of O_6T/7T/ST_10T cells, and 89.8% lesser write delay than that of CA_10T at VDD = 0.6V, indicating that the proposed 10T SRAM cell has great potential for ultra-low power applications.

BTI and Soft-Error Tolerant Voltage Bootstrapped Schmitt Trigger Circuit

This letter presents a novel BTI resilient voltage bootstrapped Schmitt trigger (VB-ST) circuit with improved noise margin, leakage power and rail-to-rail voltage. An only NMOS transistor is used in the proposed VB-ST circuit, which helps to reduce the aging effect specially Negative Bias Temperature Instability (NBTI) on the circuit. The reliability of the circuit is mainly analyzed by using the critical charge and soft error rate ratio (SERR), which indicates that the critical charge and SERR of the VB-ST circuit are improved by $6.31\times $ and reduced by 84.0%, respectively as compared to the CMOS circuit at 0.4V supply voltage. For the reliable and robust proposed circuit design, the quality factor (QF) is used as a performance metric and observed that the proposed circuit has $144\times $ improved QF as compared to the CMOS circuit.

Stable organic SRAM cell with p-type access transistors

This paper demonstrates the implementation of a static random access memory (SRAM) cell that is suitable for low-voltage organic thin-film transistors (OTFTs). SRAM is an essential component in electronic systems which can store data or instructions for various applications. We use p-type OTFTs for the access transistors to gain higher areal efficiency and better robustness than those of conventional OTFT-based SRAM construction. We verify the stability of the proposed SRAM cell and optimize the transistor sizes through SPICE simulation. Using test chip measurement, the correct write/read operation of the proposed SRAM cell is confirmed under a 10× imbalance of the on-current ratio. The proposed SRAM cell achieves a 50% area reduction and a 2.5× static noise margin improvement, compared to the existing OTFT SRAM cell design.

Low storage power and high noise margin ternary memory cells in nanoelectronics

In recent years, due to the high ability of the multi-valued logic design in nanotechnology, the interest in the design of it has been renewed. Using multi-valued logic can lead to reduction of interconnections in the chip. This study presents two novel designs of a ternary memory cell using carbon nanotube field effect transistors (CNFETs) with only one supply voltage. In the previous works, a ternary latch has been used to store the ternary value, which has a considerably more static power and lower static noise margin in comparison to a binary latch. The proposed memory cells are based on decoding the ternary value to the binary one and saving in two binary latches; in this way, the storage power is sharply decreased and the static noise margin of the proposed ternary memory cell is also increased considerably to get close to that of a binary memory cell. The results of the simulation, using the HSPICE software and the Stanford 32 nm CNFET library with the voltage of 0.9 V, demonstrated that the proposed ternary memory cell achieved significant power saving and static noise margin improvement, as compared to the previous works with the same transistor count, which was expected.

Impact of lanthanum doped zirconium oxide (LaZrO2) gate dielectric material on FinFET inverter

Abstract Fin-typed field effect transistor (FinFET) has considered a suitable device for low power and high-performance applications. The incorporation of gate dielectric lanthanum doped zirconium oxide (LaZrO2) in the 14 nm silicon on insulator (SOI) FinFET not only enhanced effective carrier mobility but also diminished the short channel effects (SCEs). The FinFET embodiment with LaZrO2 has dwindled subthreshold swing (SS), reduced drain-induced barrier lowering (DIBL), and raised on-current to off-current ratio as a contrast to SiO2-based FinFET. A remarkable enhancement of 1.18×, 11×, and 1.3× for transconductance (g m ), early voltage (V EA ), and an intrinsic gain (A V ), respectively, have been investigated. Further, LaZrO2-based n-FinFET and p-FinFET devices have devised with equal dimensions. The improved noise margin of 0.375 V using a single-fin FinFET-based inverter circuit has proven the acceptance of this device in a circuit application.

Analytical modeling for static and dynamic response of organic pseudo all-p inverter circuits

This paper presents the performance analysis of an all-p-organic pseudo-inverter circuit using dual gate organic thin film transistors. The proposed inverter design has shown significantly high performance in terms of noise margin, gain and propagation delay, leading to the design of more robust digital circuits that, too, exhibit augmented performance. The parameters of the all-p-organic pseudo-inverter are compared with those of zero-Vgs load logic (ZVLL) and dynamic load logic based conventional inverters, and a substantial improvement is found for the novel combination of a dual gate flexible TFT with a pseudo-design. Performance parameters were deeply analyzed, and we observed that the noise margin is improved by 42.8% as compared to ZVLL based conventional inverters. A bootstrap technique was implemented to further improve the performance and reduce the threshold voltage drop. The performance parameters were analyzed mathematically and compared with simulated values. The static as well as dynamic characteristics of organic pseudo-all-p inverter, with and without bootstrap technique, were observed. Static power consumption of the organic pseudo-all-p inverter was estimated. In this way, improvement of noise margin by the bootstrap circuit of the organic pseudo-inverter is characterized. The reduced threshold voltage applied to design of low power circuits enables longer power backup for various applications.

Static Noise Margin of 6T and 8T SRAM Cell in 28-nm CMOS

Integrated circuits are more prone to noise at nanolevel as they are constrained in smaller area which leads to the generation of noise signal due to supply lines and other sources. It degrades the stability and performance of the circuit. SRAM is the best example of integrated circuit. SRAM is mainly used in high performance circuits and in portable devices where we require energy efficient memory. To reduce power dissipation, we reduce supply voltage which helps in reducing static power dissipation. But at the same time, stability of memory is degraded. Hence, it is essential to keep correct functioning in the presence of a noise source. This paper shows the stability of 6T and 8T SRAM cell on the basis of static noise margin computed using Cadence Virtuoso Design Environment at 28nm CMOS technology. Cells are operated at two different voltages 1.05V and 0.5V. Results are obtained for Hold margin, Read Margin and write margin at process corner variations. Result shows that improved noise margin is obtained by reducing supply voltage. At lower voltage, noise margin should be as high as possible. In 8T we get the improved noise margin than the 6T due to decoupled read port. Hence we can say that, 8T is better than the 6T.

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories

In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling (DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI) in a drowsy cache memory. Through HSPICE simulations, we demonstrate that, as drowsy memories age, static power reduction techniques based on DVS become more effective because of reduction in subthreshold current due to BTI aging. We develop a simulation framework to evaluate tradeoffs between static power and reliability, and a methodology to properly select the “drowsy” data retention voltage. We then propose different architectures of a drowsy cache memory allowing designers to meet different power and reliability constraints. The performed HSPICE simulations show a soft error rate and static noise margin improvement up to 20.8% and 22.7%, respectively, compared to standard aging unaware drowsy technique. This is achieved with a limited static power increase during the very early lifetime, and with static energy saving of up to 37% in 10 years of operation, at no or very limited hardware overhead.

Circuit-Level Technique to Design Variation- and Noise-Aware Reliable Dynamic Logic Gates

In this paper, a novel approach to decrease the delay variations in dynamic logic topology is proposed. The proposed method is based on extending the Schmitt trigger characteristics to dynamic gates. A simple model of the proposed technique is derived to accurately approximate the extent to which variations in delay due to process, voltage, and temperature (PVT) fluctuations can be mitigated. Reliability analyses with PVT variations have been extensively performed on NAND/NOR logic implementations of the proposed methodology. Analyses reveal about 50% reduction in delay variability, with additional improvement in noise margin at an expense of slight increase in delay. The proposed approach was assessed by Monte Carlo simulations in the SPICE environment, and the analysis results support the theoretical proposal.