Improvement In Noise Margin Research Articles

Dynamic and Tunable Threshold Voltage in Organic Electrochemical Transistors

In recent years, organic electrochemical transistors (OECTs) have found applications in chemical and biological sensing and interfacing, neuromorphic computing, digital logic, and printed electronics. However, the incorporation of OECTs in practical electronic circuits is limited by the relative lack of control over their threshold voltage, which is important for controlling the power consumption and noise margin in complementary and unipolar circuits. Here, the threshold voltage of OECTs is precisely tuned over a range of more than 1 V by chemically controlling the electrochemical potential at the gate electrode. This threshold voltage tunability is exploited to prepare inverters and amplifiers with improved noise margin and gain, respectively. By coupling the gate electrode with an electrochemical oscillator, single-transistor oscillators based on OECTs with dynamic time-varying threshold voltages are prepared. This work highlights the importance of electrochemistry at the gate electrode in determining the electrical properties of OECTs, and opens a path toward the system-level design of low-power OECT-based electronics.

Design Analysis of SRAM Cell with Improved Noise Margin based on Aspect Ratio Adjustments

Design Analysis of SRAM Cell with Improved Noise Margin based on Aspect Ratio Adjustments

Analysis of static noise margin improvement for low voltage SRAM composed of nano-scale MOSFETs with ideal subthreshold factor and small variability

An ultra-low voltage performance of nanowire-transistors-based SRAM cell is investigated using the SPICE model parameters extracted from measurement data. The impact of S-factor and threshold voltage variations on the static noise margin and the minimum operating voltage is evaluated in nanowire transistor as well as in planar bulk transistor and quasi-planar bulk transistor. The performance benefits of undoped nanowire-transistor-based SRAM are measured in terms of the read stability for low voltage and low off leakage current operation.

Performance enhancement of pentacene and F16CuPc-based low-voltage devices using cross-linked blend gate dielectrics

Herein is reported the fabrication and systematic comparative analysis of low-voltage organic filed-effect transistors (OFETs) and inverters using bare ZrOx dielectrics and inorganic–organic hybrid CZB (cross-linked ZrOx/1,6-bis(trimethoxysily)hexane blend) dielectrics. Solution-processed sol–gel chemistry was employed to prepare the gate dielectrics. Two active layers of p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) were deposited on the dielectrics using the neutral cluster beam deposition method. Compared with bare ZrOx-based transistors and inverters, the CZB-based devices with low leakage current and high capacitance exhibited significantly higher hole and electron carrier mobilities of (0.12 → 1.03) and (1.3 × 10−3 → 4.9 × 10−3) cm2 (Vs)−1, respectively, and enhanced gains of (9.4 → 13.3), together with large output voltage swings and sharp inversions in the voltage transfer characteristics (VTCs). The CZB-based inverters also exhibited improved noise margins due to the higher gain and better symmetry of the VTCs compared with their bare ZrOx-based counterparts. The results indicate that on the basis of the enhanced electrical properties of CZB dielectrics and the growth of high-quality crystalline semiconducting films on CZB dielectric surfaces, such high-performance devices operating at low voltage levels are promising potential components for integrated circuits.

Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells

We present a novel SRAM technique for simultaneously enhancing the static and dynamic noise margins in six transistor cells implemented with minimum size devices using a design for manufacturability constrained layout. During each access, the word-line voltage (VWL) is internally reduced with respect to the cell and bit-line voltages that are maintained at nominal VDD. A specific VWL can be determined for each memory region, thus allowing for an adaptive approach. The benefits and drawbacks of the technique on the overall memory performance are thoroughly investigated through both simulations and experimental data. Simulations results show that this technique expands the read margin without an appreciable increase of memory area. Specifically, an improvement of 52.6% in static noise margin and a 24.5% in critical charge (parameter used to account for the dynamic stability) has been achieved with a VWL reduction of 20%. The impact of variability on SNM is reduced, while both read and write delay increase by a specific amount that should be considered as a tradeoff when setting the word-line voltage value. A 16Kbit SRAM test chip including the proposed technique has been fabricated in a 65nm CMOS technology. Silicon measurements confirm that the proposed technique improves cell stability during READ, which allows operating at relatively low values of VWL with a small impact on read time.

A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS

This brief presents a 4R/2W register file design for two-issue microprocessors with ultra-wide dynamic voltage scaling. A full-N separated read port has been proposed to save ~ 19% area and to improve 4.5 ~ 10.4 % performance of state-of-the-art 1P3N designs for subthreshold operations. In addition, a reconfigurable write scheme has been proposed to utilize the unused write port in the energy-efficient mode with single-issue execution for ~ 18% write noise margin improvement. A test chip has been designed and fabricated using the TSMC 65-nm GP process, of which a minimum operating voltage of 148 mV has been measured.

An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS

Lowering power consumption and increasing noise margin have become two central topics in every state of the art SRAM design. Due to parameter fluctuations in scaled technologies, stable operation is critical to obtain high yield low-voltage, low-power SRAM. Recent published works in literature have shown that the conventional 6T SRAM suffers a severe stability degradation due to access disturbances at low-power mode. Thus, several 8T and 10T cell designs have been reported, improving the cell stability. However, they either employ single-ended read port or require too large area. In this paper, we use a fully differential 8T SRAM that allows efficient bit-interleaving to achieve soft-error tolerance with conventional Error Correcting Code (ECC). It also consumes less power when compared to the conventional 6T design. A column-based dynamic supply voltage scheme is utilized to improve both the read noise margin and the write-ability. To verify the technique, a 128 × 64-bit of the proposed SRAM has been implemented in a standard 65 nm/1 V CMOS process. Simulation results reaffirmed that the proposed design has 2× higher noise margin and consumes 54% less power when compared to the conventional 6T design.

Unipolar Organic Transistor Circuits Made Robust by Dual-Gate Technology

Dual-gate organic transistor technology is used to increase the robustness of digital circuits as illustrated by higher inverter gains and noise margins. The additional gate in the technology functions as a VT-control gate. Both zero-VGS-load and diode-load logic are investigated. The noise margin of zero- VGS-load inverter increases from 1.15 V (single gate) to 2.8 V (dual gate) at 20 V supply voltage. Diode-load logic inverters show an improvement in noise margin from ~0 V to 0.7 V for single gate and dual gate inverters, respectively. These values can be increased significantly by optimizing the inverter topologies. As a result of this optimization, noise margins larger than 6 V for zero- VGS-load logic and 1.4 V for diode-load logic are obtained. Functional 99-stage ring oscillators with 2.27 μs stage delays and 64 bit organic RFID transponder chips, operating at a data rate of 4.3 kb/s, have been manufactured.

Applications of impact-ionization metal–oxide-semiconductor (I-MOS) devices to circuit design

In this paper, the applicability of impact-ionization metal–oxide-semiconductor (I-MOS) devices has been discussed to some circuits such as static inverters, static NAND gates, static NOR gates, and 6T-SRAM cells. Based on detailed circuit analysis, some critical issues are overcome: cascadability, power consumption, series connection, and unidirectional output current. Complementary I-MOS (CI-MOS) inverters show higher noise margin and lower crowbar current than CMOS ones, which leads to the reduction of supply voltage and short-circuit power dissipation, respectively. In the case of static NAND and NOR gates, the CI-MOS also shows improved noise margin. Finally, CI-MOS 6T-SRAM cells show 22.6% improvement in SNM without much penalty in cell area compared with CMOS ones.

Exploiting Hysteresys in MCML Circuits

In this brief, hysteresis is introduced to improve the noise margin of positive-feedback source-coupled logic (PFSCL) gates, that are a modification of MOS current-mode logic recently proposed by the same authors. To better understand the effect of hysteresis on the performance and the design of these circuits, a simple analytical model of the noise margin is developed. Extensive simulations on a 0.18-mum CMOS process confirm the adequate accuracy of the model. The noise margin improvement due to the hysteresis is then exploited to reduce the logic swing, which can be beneficial in terms of the speed performance or the power consumption. Practical cases where hysteresis is advantageous are identified, and a comparison with PFSCL gates without hysteresis is carried out. Simulations confirm that, in some well-defined cases, hysteresis can significantly reduce the gate delay under a power constraint, or achieve a power saving under a speed constraint. As a fundamental result, hysteresis turns out to be an interesting design option to improve the power efficiency of PFSCL gates

Multilevel Signal Processing Technique for a 30 Gbit/inch2 Phase-Change Optical Disk System

We developed a multilevel recording technique and a Viterbi decoding technique for increasing the recording density of a phase-change optical disk. In this multilevel recording technique, each mark recorded on the disk changes its edge position in four steps according to four-level data. Since two consecutive mark edges are reproduced simultaneously, their reproduced signal takes seven levels. We devised a Viterbi decoder with reference matrices in order to improve data detection performance by compensating the nonlinearity of this multilevel signal. We evaluated the error rate performance of this optical disk system by computer simulation. The Viterbi decoder with the reference matrices showed superior performance, and had an improved noise margin which is 3.5 dB higher than that of a conventional Viterbi decoder. By employing the multilevel recording technique and the Viterbi decoding technique, we confirmed the feasibility of the phase-change optical disk system with a recording density of 30 Gbit/inch2.

Enhancement of metal–semiconductor barrier height with superthin silicon dioxide films deposited on gallium arsenide by liquid phase deposition

This study presents a method for surface passivation using silicon dioxide (SiO2). The proposed method has shown great effectiveness on metal–semiconductor barrier height enhancement. A high quality SiO2 layer is developed via liquid phase deposition, a method which naturally leaves a doping-level fluorine residue in the SiO2. The addition of fluorine to enhance the Schottky barrier height (SBH) is first discussed. Experimental results are presented. It is found that this fluorine addition enhances the Schottky barrier height, which allows a larger positive gate bias for enhancement mode metal–semiconductor field-effect transistors, thus permitting the fabrication of digital logic circuits with improved noise margins and relaxed tolerance with regard to device threshold voltage uniformity. The SBH to n-gallium arsenide (GaAS) is found to be approximately 0.7 eV. Finally, the effective barrier height of the metal–insulator–semiconductor structure reached 1.03 eV after annealing. The enhancement of SBH has been attributed to the formation of these stable interface layers. A model for fluorine-enhanced SiO2 SBH enhancement is also presented.

Large-scale complementary integrated circuits based on organic transistors

Thin-film transistors based on molecular and polymeric organic materials have been proposed for a number of applications, such as displays and radio-frequency identification tags. The main factors motivating investigations of organic transistors are their lower cost and simpler packaging, relative to conventional inorganic electronics, and their compatibility with flexible substrates. In most digital circuitry, minimal power dissipation and stability of performance against transistor parameter variations are crucial. In silicon-based microelectronics, these are achieved through the use of complementary logic-which incorporates both p- and n-type transistors-and it is therefore reasonable to suppose that adoption of such an approach with organic semiconductors will similarly result in reduced power dissipation, improved noise margins and greater operational stability. Complementary inverters and ring oscillators have already been reported. Here we show that such an approach can realize much larger scales of integration (in the present case, up to 864 transistors per circuit) and operation speeds of approximately 1 kHz in clocked sequential complementary circuits.

Charge recycling differential logic (CRDL) for low power application

A novel logic family, called charge recycling differential logic (CRDL), has been proposed and analyzed. CRDL reduces power consumption by utilizing a charge recycling technique with the speed comparable to those of conventional dynamic logic circuits. It has an additional benefit of improved noise margin due to inherently static operation. The noise margin problem of true single-phase-clock latch (TSPC) is also eliminated when a CRDL logic circuit is connected to it. Two swing-suppressed-input latches (SSILs), which are introduced for use with CRDL, have better performance than the conventional transmission gate latch. Moreover, a pipeline configuration with CRDL in a true two-phase clocking scheme shows completely race-free operation with no constraints on logic composition. Eight-bit Manchester carry chains and full adders were fabricated using a 0.8 /spl mu/m single-poly double-metal n-well CMOS technology to verify the relative performance of the proposed logic family. The measurement results indicate that about 16-48% improvements in power-delay product are obtained compared with differential cascode voltage switch (DCVS) logic.

2.5 Gb/s laser-driver GaAS IC

A laser-diode driver GaAs IC incorporating an optional NRZ/RZ (non-return-to-zero/return-to-zero) conversion facility, having ECL (emitter-coupled logic) and SCFL (source-coupled FET logic)-compatible inputs and providing a 0-60-mA adjustable output current into a 50- Omega /5-V termination at bit rates up to 2 Gb/s NRZ and maintaining a clear eye opening of 50 mA at 2.5 Gb/s NRZ bit rate has been designed, using a commercial 1- mu m gate-length (F/sub tau /=12 GHz) GaAs MESFET foundry service. The high maximum output current is obtained by implementing the output driver as a cascode differential amplifier. The logic circuitry implemented using a novel, DCAL (diode-clamped active-load) SCFL family, which is based on gate-width scaling rather than on absolute values, so that the on-chip logic voltage swing is less sensitive to process variations than conventional SCFL. A 60% improvement in noise margin is also obtained. To verify laser driving performance a back-to-back optical-fiber transmission experiment was performed, giving good optical eye diagrams at 2.5 Gb/s. The electrooptical interplay between laser-diode driver and laser-diode has been demonstrated using SPICE simulations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Neuron MOS binary-logic integrated circuits. II. Simplifying techniques of circuit configuration and their practical applications

For pt.I see ibid., vol.40, no.3, p.570-6 (March 1993). The fundamental circuit ideas developed by the authors in Part I are applied to practical circuits, and the impact of neuron MOSFET on the implementation of binary-logic circuits is examined. For this purpose, two techniques are presented to simplify the circuit configurations. It is shown that the input-stage D/A converter circuit in the basic configuration can be eliminated without any major problems, resulting in improved noise margins and speed performance. Then a design technique for symmetric functions, which is especially important when the number of input variables increases, is presented. The nu MOS logic design is characterized by a large reduction in the number of transistors as well as of interconnections. However, the decrease in transistor count comes at a cost in process tolerance due to the multivalued nature of the device operation. Test circuits were fabricated by a typical double-polysilicon CMOS process, and the measurement results are presented. >

Novel circuit technology for ECL-compatible GaAs static RAMs with small access time scattering

A novel circuit technology has been developed to realize GaAs SRAMs suitable for use in real-system environments. It has achieved Si ECL compatibility through the use of an ECL 100 K-compatible input buffer circuit with on-chip reference compensation. Wide V/SUB th/ tolerance and an improved noise margin have been obtained through the use of a novel normally-on-type circuit called the FET logic with Schottky diode and coupling capacitor (FLSC). Two experimental ECL-compatible GaAs SRAMs (256-word/spl times/4-b and 1024-word/spl times/4-b) were designed and successfully fabricated using this technology. In the 4 K SRAM, an access time of 2.2-3.0 ns with a power dissipation of 890 mW was achieved and the normal read/write operation at 4-ns cycle time was also confirmed.