Effect of back gate biasing in negative capacitance field effect transistor

Abstract

In this paper, we have studied the effect of back gate bias technique in negative capacitance field effect transistor. In N-NCFET, OFF current decreases and threshold voltage increases with positive back gate bias, while with negative back gate bias, OFF current increases and threshold voltage decreases. This behavior of back gate bias in N-NCFET is quite different as compared to N-MOSFET. The primary reason behind this contradictory behavior is the dependence of internal node voltage (VMOS) on the body terminal of N-NCFET via bulk coupling factor. Further, we have utilized this property to design NCFET based inverter.Various figure of merits like noise margin, delay, static power dissipation and dynamic power dissipation is studied for the designed inverter. The designed inverter with suggested back gate bias shows 16% and 13.9% improved noise margin, and reduced delay performance respectively as compared to conventional NCFET without bias. Also, the power dissipation parameter (static and dynamic) is reduced by 90.1% and 3.8% respectively. We have also seen the effect of channel length scaling in the NCFET, decrement in the channel length improves the gate stack capacitance of NCFET which leads to decrement in OFF current at lower technology node.