Low storage power and high noise margin ternary memory cells in nanoelectronics

Abstract

In recent years, due to the high ability of the multi-valued logic design in nanotechnology, the interest in the design of it has been renewed. Using multi-valued logic can lead to reduction of interconnections in the chip. This study presents two novel designs of a ternary memory cell using carbon nanotube field effect transistors (CNFETs) with only one supply voltage. In the previous works, a ternary latch has been used to store the ternary value, which has a considerably more static power and lower static noise margin in comparison to a binary latch. The proposed memory cells are based on decoding the ternary value to the binary one and saving in two binary latches; in this way, the storage power is sharply decreased and the static noise margin of the proposed ternary memory cell is also increased considerably to get close to that of a binary memory cell. The results of the simulation, using the HSPICE software and the Stanford 32 nm CNFET library with the voltage of 0.9 V, demonstrated that the proposed ternary memory cell achieved significant power saving and static noise margin improvement, as compared to the previous works with the same transistor count, which was expected.