Impact Of Interface Trap Charges Research Articles

Interfacial charge and temperature analysis of gate-all-around line tunneling TFET for improved device reliability

In this article, the impact of interface-trap charges (ITCs) on the DC and analog/RF parameters of gate-all-around vertical TFET (GAA-VTFET) are considered to evaluate the reliability of the device. ITCs are included at oxide/semiconductor interface of GAA-VTFET where the probability of occurrence of traps are high owing to faults in the manufacturing process. A detailed investigation is carried out by tuning the temperature, polarities and density of ITCs. It is clearly observed from TCAD based simulation results that the presence of traps alters the flat-band voltage, thereby affecting the overall performance of the device. Transfer characteristics of the device depicts that impact of traps shows more variation in the OFF-state current than the ON-current. However, presence of donor traps improves the analog/RF parameter, such as parasitic capacitances (Cgg), Transconductance (gm), cut-off frequency (fT), output resistance (Rout) etc. Furthermore, the simulation results proclaim that GAA-VTFET shows more resilient to acceptor traps than the positive traps. Moreover, by examining the influence of ambient temperature on device performance, it is revealed that the drain current in the subthreshold region (at low gate bias) is more susceptible to the degradation than the super-threshold region at elevated temperature. This is mainly due to the superiority of the trap-assisted tunneling (TAT) and Shockley-Read-Hall (SRH) recombination mechanisms over the band-to-band tunneling (BTBT). When the raise in ambient temperature is tuned between minimum of 200 K to maximum of 400 K, it is observed that OFF-current increases by ∼7 times. Lastly, voltage-transfer characteristics (VTC) analysis of the resistive-load inverter clearly demonstrates that the influence of traps on the noise margin is within acceptable limits.

Impact of Interface Trap Charges on Silicon Carbide (4H-SiC) Based Gate – Stack, Dual Metal, Surrounding Gate, FET (4H-SiC- GSDM-SGFET) for Analog and Noise Performance Analysis for 5 G/LTE Applications

This article examines the impact of various interface trap charges on silicon carbide-based gate—stack, dual metal, surrounding gate, FET (4H-SiC-GSDM-SGFET). It has been contrasted for performance with silicon carbide (4H-SiC)-based dual metal, surrounding gate, FET (4H-SiC-DM- SGFET). For both devices, output characteristics including transconductance (gm), output conductance (gd), drain current (Ids), gate capacitance (Cgg), cutoff frequency (fT) and threshold voltage (Vth) have been examined. Surface potential and electron concentration were also inspected using a contour plot for both the device structures. A gate-stack with a high k- dielectric, Lanthanum oxide (La2O3) along with gate dielectric layer Aluminum oxide (Al2O3) was used for proposed structure implementation. Additionally, we investigated how trap charges affect noise figure (NF) and noise conductance (NC). Also, a CMOS inverter has been developed and its output characteristics have been compared for both the device architectures. ATLAS 3-D device simulator has been employed to conduct the simulations.

Analysis of the Impact of Interface Trap Charges on the Analog/RF Performance of a Graphene Nanoribbon Vertical Tunnel FET

Analysis of the Impact of Interface Trap Charges on the Analog/RF Performance of a Graphene Nanoribbon Vertical Tunnel FET

Impact of interface trap charges on analog/RF and linearity performances of PGP negative capacitance FET

Here, we examine the impact of various trap charges on the baseline and NC PGPFET (negative capacitance partial ground plane FET) by applying localized charges (donor/acceptor) at the semiconductor/insulator interface. Examining different parameters has revealed that donor traps enhance device characteristics while acceptor traps reduce device performance. Therefore NC effect is generated by introducing a ferroelectric material in the gate stack that enhances the device performance by the voltage amplification process. Doped HfO2 is taken as the ferroelectric material because of its high dielectric capacitance and reliable polarization rate. Along with DC, RF/Analog factors such as trans-conductance (gm), output conductance (gds), trans-conductance generation factor (TGF), cut-off frequency (ft), trans-conductance frequency product (TFP) have been examined for the potential use of NCFET for RF applications. Additionally, linearity parameters like gm2, gm3, VIP2, VIP3 and intermodulation distortion (IMD3) is also compared for both traps. Due to its improved performance, NC PGPFET is appropriate for low-voltage analog/RF applications.

Potential model and simulation analysis of dual material gate vertical TFET with impact of interface trap charges

This paper presents modeling and simulation of the dual material gate vertical tunnel FET (VTFET-DMG) by including the interface trap charges. The interface trap charges are considered at the high-k and silicon substrate interface near the source and the channel region. The surface potential model is developed here by utilizing the 1-D and 2-D Poisson equations solved with different boundary conditions after dividing the whole device into eight different regions. The parabolic approximation is assumed to find the numerical solution of the Poisson equations. The same device is also designed and simulated in the Silvaco TCAD simulator with the inclusion of the impact of the interface trap charges and the outcomes of the simulations are compared with the modeled results. The variation of the surface potential with the increase in positive interface charges and negative interface charges is plotted and analyzed. It is seen that the surface potential enhances with the increase in positive interface charges and it reduces with the increase in the negative interface trap charges. We use the dual material gate approach in proposed structure to show an overall increase in the performance of the device. Incorporating the high-K gate oxide in the presence of interface traps improves the device's reliability for low power utilization.

Analysis on electrical parameters including temperature and interface trap charges in gate overlap Ge source step shape double gate TFET

In this paper, the electrical parameters are evaluated for the variations of temperature in Gate Overlap Ge source Step Shape Double Gate TFET (GO-Ge-SSDG-TFET) under the impact of interface trap charges (ITCs). Here, the effect of positive ITC (PITC) and negative ITC (NITC) with wide variation in trap concentrations along with variation in temperature (200–500 K) on DC, RF/analog, and linearity behavior are studied using TCAD simulator. It is found that there is up-gradation (degradation) in current ratio (ION/IOFF, ION/IAMBP), cut-off frequency (ft), and linearity parameters with PITC (NITC). At low gate voltage, there is degradation in OFF-state behavior with increased temperature and this is due to exponential dependence of temperature with Shockley-Read-Hall (SRH) recombination. Moreover, at high gate bias, Band to Band tunneling (BTBT) is dominant, which is weak temperature dependence and leads to negligible variation in drain current. The OFF state current is degraded by the order of 109 as temperature is increased from 200 to 500 K. At high temperature, the up-gradation in ft and intrinsic delay (τ) indicates improvement in device characteristic.

Impact of Interface Trap Charges on the Performances of Junctionless MOSFET in Sub-Threshold Regime

Interface trap charge (ITC) can induce device reliability issues in long/short channel junctionless (JL) MOSFET. The impact of positive (donor)/ negative (acceptor) ITC on the power and delay of the JL MOSFET circuits in the sub-threshold regime has been analyzed here. The presence of ITC and trap occupational probability variation modulates the threshold voltage of the device which also can affect the device/ circuits performances. So, the Power, Delay and Power delay products of JL-MOSFET have been modeled analytically first and then validated using the device simulator. For Device Simulation and modeling, SILVACO ATLAS and MATLAB have been used respectively. Extensive simulations show the accuracy of the proposed modeled data. Also, the optimum supply voltage is shifted in presence of the ITC. This framework will help the researchers to understand the device reliability issues and their limitations due to the ITC in sub-threshold ultra-large scale of integration applications.

Assessment of Interface Trap Charges on Proposed TFET for Low Power High-Frequency Application

Accumulation of trap charges at the semiconductor and oxide interface is the most dominating factor and cannot be neglected as it degrades device performance and reliability. This manuscript, presents detailed investigation to analyze the impact of interface trap charges (ITCs) on the performance parameters of the proposed device i.e., heterogeneous dielectric dual metal gate step channel TFET (HD DMG SC-TFET). The comparative study is conducted with dual metal gate step channel TEFT (DMG SC-TFET). The proposed device shows improved current carrying capability, suppressed ambipolar behaviour with steeper subthreshold swing. The purpose of this study to determine the ITCs impact on DC characteristics and analog/RF electrical performance parameters of the proposed device. It further observed that the proposed device exhibit superior performance due to dielectric engineering at oxide layer. Moreover, advanced communication devices must respond linearly therefore, the impact of ITCs on linearity parameters is also studied. From this brief comparative investigation, it is observed that the proposed TFET exhibits negligible distortion in linearity parameters with little or no impact of trap charges as compared to DMG SC-TFET. Thus, proposed TFET is appropriate for ultra-low power high-frequency electronic devices.

A Reliability Study of Non-uniform Si TFET with Dual Material Source: Impact of Interface Trap Charges and Temperature

The article reports the extraction of DC characteristics and small signal parameters of Non-uniform Si TFET with dual material source (NUTFET-DMS) at different frequencies followed by its reliability investigation. The reliability of the device is examined by analysing: (1) the impact of the presence of interface trap charges, (2) the impact of temperature variation (200- 400 K). In the analysis it has been observed that in case of absence of interface trap charges the increase in frequency reduces the value of parasitic capacitances. In addition, the presence of interface trap charges lessens the value of parasitic capacitances up to a certain gate to source voltage after that it shows a reverse effect. Further, it has been perceived that the effect of change in temperature is more on device ambipolar current when interface trap charges are present, whereas the reverse is true in the case of OFF state current and different parasitic capacitances.

A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET

In this work, the impact of interface trap charges (ITCs) on electrical characteristics of dielectric pocket SOI-TFET (DP SOI-TFET) proposed for the reduction of ambipolar conduction and improvement of high-frequency (HF) performances has been demonstrated in details. The reliability of DP SOI-TFET has been examined by analysing the impact of varying polarity and density of ITCs on dc and analog/HF performances of the proposed device. Through TCAD simulations, it has been shown that donor and acceptor ITCs existing at the interface between drain region and dielectric pocket (i.e. Si/DP) have significant impact on the parameters such as OFF-state current, ambipolar conduction, parasitic capacitances, output resistance, and cut-off frequency of DP SOI-TFET. Furthermore, a comparative analysis has been carried out between the conventional and DP SOI-TFET under influence of traps, and it has been found that performances of the proposed device are further improved by the existence of acceptor ITCs at higher negatively biased gate. Even though, the existence of donor ITCs at Si/DP interface has been found degrading the performances of the proposed DP SOI-TFET, simulation results suggest that dc and analog/HF figure of merits are still superior in the proposed device as compared to those in the conventional SOI-TFET.

Interface trap charge-based reliability assessment of high-k dielectric-modulated nanoscaled FD SOI MOSFET for low power digital ICs: Modeling and simulation

This paper proposes the analytical surface potential and threshold-voltage model for performance investigation of gate stack (GS) dual-metal-insulated-gate (DMIG) source-engineered (SE) Fully-depleted silicon-on-insulator (FD SOI) MOSFET for low-power digital applications. In which, a new concept of dielectric-modulated high-k insulator-gap with source engineering has been analytically formulated for the first time in dual-metal-gate technology-based FD SOI MOSFET. The surface potential model is developed using two-dimensional Poisson's equations with including effects of interface trap charges (ITCs) and verified against numerical simulations over the TCAD tool from Silvaco ATLAS™. Also, the parametric analysis has been performed to optimize the device dimensions for better nanoscaled MOS design. Further, a six transistor (6-T) SRAM cell is designed using n/p-GS-DMIG SE FD SOI MOSFET for the analysis of static-noise-margin (SNM). It is observed that the proposed FD SOI MOSFET offers excellent immunity towards short-channel-effects (SCEs) along with improved SRAM circuit performance at different ITC conditions. • Impact of interface Trap Charges (ITCs) on GS-DMIG SE FD SOI MOSFET. • Analytical Modeling of Surface Potential and Threshold Voltage of GS-DMIG SE FD SOI MOSFET. • Analysis of DIBL effect at different ITC Conditions. • Comparative analysis of proposed FD SOI MOSFET in nanoscale regime. • Design and Analysis of 6T-SRAM cell using n-/p-GS-DMIG SE FD SOI with including effects of ITCs.

Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally stacked gate oxide

This work reports the impact of interface trap charges (ITCs) on the electrical performance characteristics of a source pocket engineered (SPE) Ge/Si heterojunction (HJ) vertical TFET (V-TFET) with an HfO2/Al2O3 laterally stacked heterogeneous gate oxide (LSHGO) structure. SILVACO ATLAS™ 3-D TCAD tool has been used to compare various electrical performance parameters which includes DC parameters (i.e. ION, IOFF, ION/IOFF and subthreshold swing), RF figures of merit (i.e. transconductance, output conductance, cut-off frequency, the maximum frequency of oscillation, transit time, gain bandwidth product, transconductance generation factor (device efficiency) and transconductance frequency product) and linearity figures of merit (i.e. gm2, gm3, Third order voltage intercept point (VIP3), third intercept input power (IIP3), third order intermodulation distortion power (IDM3), 1-dB compression point and zero crossover point (ZCP)) of the proposed Ge/Si SPE-HJ-LSHGO-V-TFET with their corresponding values of SPE-HJ-V-TFET with only Al2O3 as the gate oxide for both donor (+ve) and acceptor (−ve) interface trap charges at the gate oxide/channel interface. The reported study shows that the proposed HfO2/Al2O3 based SPE-HJ-LSHGO-V-TFET device is more immune to ITCs than the SPE-HJ-V-TFET device with only Al2O3 as the gate oxide.

Performance investigation of a novel GaAs1-xSbx-on-insulator (GASOI) FinFET: Role of interface trap charges and hetero dielectric

In this paper, for the first time we proposed a novel GaAs1-xSbx-on-Insulator (GASOI) FinFET on GaAS substrate using well calibrated simulation models. Impact of this novel channel material GaAs1-xSbx in FinFET performance is thoroughly investigated and optimized accordingly. The acquired results of the proposed device show a significant improvement in ON current with smaller OFF current, which in turn boosts ION/IOFF ratio as compared to the earlier reported InGa1-xAsx and InGa1-xSbx FinFET. A maximum transconductance (gm) of ∼1.3 mS/μm is achieved that signifies a higher intrinsic gain of the proposed device. The performance optimization can be done by varying various device dimensional parameters such as width and height of the Fin, channel length, along with the gate metal work-function. We have also investigated the impact of interface trap charges in the device performance and to mitigate the effect of random dopants, a novel idea to implement a Hetero Buried Oxide (BOX) layer over the GaAs1-xSbx SOI FinFET is discussed.

Performance Tuning and Reliability Analysis of the Electrostatically Configured Nanotube Tunnel FET with Impact of Interface Trap Charges

This paper examines, an electrostatically configured Nano-Tube Tunnel Field-Effect Transistor (ED-NTTFET). During the fabrication process, different charges such as fixed charge, oxide trapped charge, and interface trapped charge have been produced at the gate oxide interface. So the effect of positive and negative interface trapped charge (+ITC & -ITC) has been proposed for the first time for electrostatic doped-based Nano-Tube TFET (ED-NTTFET). There are two types of techniques, charge plasma (EP) based technique and electrostatic doped (ED) technique is used to produce the induced charge in the intrinsic channel region. In the charged plasma (CP) technique, the metal work-function is used to produce the induced charge while in the electrostatic doped (ED) technique electrostatic voltage is applied across the source and drain side to produce the induced charge in the intrinsic channel region. Analysis of the various device parameters such as hole/electron concentration, energy diagram, electric field, tunneling rate, driving current, OFF current, ON current, ION/IOFF, threshold voltage, and average sub-threshold slope in the presence of interface trapped charge (ITC). Due to positive interface trapped charge electric field and band to band tunneling rates are improved. So the drain current of the device also improved from the 2.94*10−5 A/um2 to 5.35*10−5A/um2. Linearity parameters such as second & third order trans-conductance (gm2 & gm3), second & third order voltage intercept point (VIP2 & VIP3), second & third order harmonics distortions (HD2 & HD3) and intermodulation distortions (IMD) have been discussed. The negative interface trapped charge (-ITC) degrades the linearity parameter of the device and the positive interface trapped charge (+ITC) improves the linearity parameter of the device. The proposed electrostatic doped nano-tube TFET (ED-NTTFET) produced higher cut-off frequency at lowers operating gate voltage.

Impact of trap charge and temperature on DC and Analog/RF performances of hetero structure overlapped PNPN tunnel FET

Impact of interface trap charges (ITCs) as well as temperature on the performance of a proposed dual dielectric constant spacer source/drain, overlapped double gate tunnel FET with a source pocket was investigated using two-dimensional Technology Computer-Aided Design (TCAD) device simulator. The proposed device is Si-based with Germanium as the source material, SiGe as a pocket material, and has a high-k gate dielectric. Its performance in terms of DC and analog/RF parameters vis-a-vis a conventional double gate PNPN TFET was compared. The device shows better results than the conventional one with an ON current of 1.71 × 10−3 A/µm, ON–OFF current ratio 1011, and subthreshold swing of 45 mV/decade. The study was focused on the analysis of the electric field, transfer characteristics, transconductance (gm), output conductance (gd), parasitic capacitances, gain-bandwidth product (GBP), cut off frequency (fT) for both the damaged (presence of donor/acceptor interface trap charges) and undamaged (no trap) conditions. The study revealed that the proposed structure is more immune to the interfacial trap charges as compared to the conventional device. Apart from this, the analysis shows a degradation of subthreshold swing (SS) and OFF current (IOFF) at elevated temperatures.

Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate

This paper reports the TCAD based investigation of the DC/RF and linearity characteristics of a newly proposed dual-material (DM) laterally-stacked (LS) SiO2/HfO2 heterojunction-TFET-on-SELBOX substrate (LS-STFET). Device-level performance comparison is made between the proposed TFET with a dual-material (DM) vertically-stacked (VS) SiO2/HfO2 heterojunction-TFET-on-SELBOX substrate (VS-STFET). Low bandgap material Ge is used in the source region to form a Ge (source)/Si (channel) heterojunction for enhancing the ON-state current of the presented TFETs. The effects of both donor (+ ve) and acceptor (−ve) type interface trap charges at the channel/SiO2 region on the DC, analogue/RF and linearity figure of merits have been analyzed for both the devices under study. The LS-STFET is shown to possess higher ON-state current and smaller subthreshold swing (SS) over the VS-STFET. In addition, the LS-STFET is shown to have better DC, analog/RF and linearity performance over VS-STFET in the presence of the donor and acceptor interface trap charges.

Comparative Analysis of the Effects of Trap Charges on Single- and Double-Gate Extended-Source Tunnel FET with δp+ SiGe Pocket Layer

This paper investigates the trap analysis of a double-gate extended-source tunnel field-effect transistor (DG-ESTFET) and single-gate extended-source tunnel field-effect transistor (SG-ESTFET) with a δp+ SiGe pocket layer. The trap analysis of both structures is compared in terms of the currents, average subthreshold swing, threshold voltage, and switching ratio. In addition, the impact of interface trap charges at different interfaces on analog/RF performance, transfer characteristics, and slope are investigated and compared. It is observed that the trap charges between the silicon and front gate oxide interface (Si–HfO2) have a greater effect on the DG-ESTFET than the SG-ESTFET, whereas the reverse is true when trap charges are at the back gate oxide interface (Si–SiO2). In the case of analog/RF performance, the SG-ESTFET is found to be more affected by the trap charges at the silicon and front gate oxide interface (Si–HfO2).

Reliability Assessment of GaAs/Al₂O₃ Junctionless FinFET in the Presence of Interfacial Layer Defects and Radiations

This research work reports reliability assessment of junctionless (JL) FinFET in the presence of interfacial trap charges and radiations. The degradation in performance of JL FinFET is evaluated by calculating various figure of merit. Linearity behavior of the device is studied by considering higher order coefficient of transconductance, VIP2, VIP3, IIP3, IMD3. Also, a comparative analysis of various structures obtained by considering different semiconductor/oxide combinations is performed. Impact of interface trap charges and radiations on performance of these devices is carried out in detail. Results show that, the structure having higher value dielectric oxide provides better immunity to trap charges. The mechanism of Single event transients is also studied in JL FinFET and result show that the peak value of transient current increases with increase in LET values.

GaAs0.5Sb0.5/ In0.53Ga0.47As heterojunction dopingless charge plasma-based tunnel FET for analog/digital performance improvement

Abstract A dual side doping-less (DL) GaAs0.5Sb0·5/In0.53Ga0.47As heterojunction tunnel FET (DDL-HTFET) configuration together with hetero-gate-dielectric material (HfO2/SiO2) has been proposed in this article. Hence, N+-pocket with varying electron concentration has been implemented by changing the length of source-side channel (LSC) beneath the gate. The impact of interface trap charges (ITCs) on the execution of the proposed device has been examined by initiating dual (donor and acceptor) sort of confined charges near the semiconductor/insulator intersection. An assessment has been carried out among proposed HTFET and Si-based devices having similar dimensions with respect to dc, analog/RF, and linearity distortion factors thoroughly in existence of ITCs. ATLAS simulations illustrate that the proposed DDL-HTFET is more protected in terms of performance deviation than its Si-based contenders with various ITCs existing at semiconductor/insulator intersection. Hence, DDL-HTFET model can be a promising candidate for the low-power RF applications and can offer improved linearity and less distortion.

Impact of Interface Trap Charges on Analog/RF and Linearity Performances of Dual-Material Gate-Oxide-Stack Double-Gate TFET

This paper investigates the impact of different interface trap charges (ITCs) on dual-material gate-oxide-stack double-gate TFET (DMGOSDG-TFET) by introducing localized charges (donor/acceptor) at the interface of semiconductor/insulator. For this, we have observed the effects of different ITCs on both conventional dual material control gate tunnel field effect transistor (DMCG-TFET) and dual-material gate-oxidestack double-gate TFET with identical dimensions in terms of DC, analog/RF and linearity performance parameters. Both the devices with positive (donor) and negative (acceptor) ITCs, have been simulated using technology computer-aided design (TCAD) tool. To understand the impact of different ITCs on the DC and analog/RF performances, the parameters such as electric field, transfer characteristics, transconductance, parasitic capacitance, fT, GBP and TFP for DMGOSDG-TFET have been analyzed and compared with that of DMCG-TFET. Further, to analyze the effect of different ITCs on the linearity performances, the parameters VIP2, VIP3, IIP3 and IMD3 have been investigated and compared with that of the conventional DMCG-TFET. Simulation results demonstrate that DMGOSDG-TFET is more immune towards different types of ITCs as compared to the conventional DMCG-TFET. Hence, DMGOSDG-TFET is more reliable over the conventional device for ultra low power applications.