Potential model and simulation analysis of dual material gate vertical TFET with impact of interface trap charges

Abstract

This paper presents modeling and simulation of the dual material gate vertical tunnel FET (VTFET-DMG) by including the interface trap charges. The interface trap charges are considered at the high-k and silicon substrate interface near the source and the channel region. The surface potential model is developed here by utilizing the 1-D and 2-D Poisson equations solved with different boundary conditions after dividing the whole device into eight different regions. The parabolic approximation is assumed to find the numerical solution of the Poisson equations. The same device is also designed and simulated in the Silvaco TCAD simulator with the inclusion of the impact of the interface trap charges and the outcomes of the simulations are compared with the modeled results. The variation of the surface potential with the increase in positive interface charges and negative interface charges is plotted and analyzed. It is seen that the surface potential enhances with the increase in positive interface charges and it reduces with the increase in the negative interface trap charges. We use the dual material gate approach in proposed structure to show an overall increase in the performance of the device. Incorporating the high-K gate oxide in the presence of interface traps improves the device's reliability for low power utilization.