Abstract
Interface trap charge (ITC) can induce device reliability issues in long/short channel junctionless (JL) MOSFET. The impact of positive (donor)/ negative (acceptor) ITC on the power and delay of the JL MOSFET circuits in the sub-threshold regime has been analyzed here. The presence of ITC and trap occupational probability variation modulates the threshold voltage of the device which also can affect the device/ circuits performances. So, the Power, Delay and Power delay products of JL-MOSFET have been modeled analytically first and then validated using the device simulator. For Device Simulation and modeling, SILVACO ATLAS and MATLAB have been used respectively. Extensive simulations show the accuracy of the proposed modeled data. Also, the optimum supply voltage is shifted in presence of the ITC. This framework will help the researchers to understand the device reliability issues and their limitations due to the ITC in sub-threshold ultra-large scale of integration applications.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
