Analysis on electrical parameters including temperature and interface trap charges in gate overlap Ge source step shape double gate TFET

Abstract

In this paper, the electrical parameters are evaluated for the variations of temperature in Gate Overlap Ge source Step Shape Double Gate TFET (GO-Ge-SSDG-TFET) under the impact of interface trap charges (ITCs). Here, the effect of positive ITC (PITC) and negative ITC (NITC) with wide variation in trap concentrations along with variation in temperature (200–500 K) on DC, RF/analog, and linearity behavior are studied using TCAD simulator. It is found that there is up-gradation (degradation) in current ratio (ION/IOFF, ION/IAMBP), cut-off frequency (ft), and linearity parameters with PITC (NITC). At low gate voltage, there is degradation in OFF-state behavior with increased temperature and this is due to exponential dependence of temperature with Shockley-Read-Hall (SRH) recombination. Moreover, at high gate bias, Band to Band tunneling (BTBT) is dominant, which is weak temperature dependence and leads to negligible variation in drain current. The OFF state current is degraded by the order of 109 as temperature is increased from 200 to 500 K. At high temperature, the up-gradation in ft and intrinsic delay (τ) indicates improvement in device characteristic.