Interfacial charge and temperature analysis of gate-all-around line tunneling TFET for improved device reliability

Abstract

In this article, the impact of interface-trap charges (ITCs) on the DC and analog/RF parameters of gate-all-around vertical TFET (GAA-VTFET) are considered to evaluate the reliability of the device. ITCs are included at oxide/semiconductor interface of GAA-VTFET where the probability of occurrence of traps are high owing to faults in the manufacturing process. A detailed investigation is carried out by tuning the temperature, polarities and density of ITCs. It is clearly observed from TCAD based simulation results that the presence of traps alters the flat-band voltage, thereby affecting the overall performance of the device. Transfer characteristics of the device depicts that impact of traps shows more variation in the OFF-state current than the ON-current. However, presence of donor traps improves the analog/RF parameter, such as parasitic capacitances (Cgg), Transconductance (gm), cut-off frequency (fT), output resistance (Rout) etc. Furthermore, the simulation results proclaim that GAA-VTFET shows more resilient to acceptor traps than the positive traps. Moreover, by examining the influence of ambient temperature on device performance, it is revealed that the drain current in the subthreshold region (at low gate bias) is more susceptible to the degradation than the super-threshold region at elevated temperature. This is mainly due to the superiority of the trap-assisted tunneling (TAT) and Shockley-Read-Hall (SRH) recombination mechanisms over the band-to-band tunneling (BTBT). When the raise in ambient temperature is tuned between minimum of 200 K to maximum of 400 K, it is observed that OFF-current increases by ∼7 times. Lastly, voltage-transfer characteristics (VTC) analysis of the resistive-load inverter clearly demonstrates that the influence of traps on the noise margin is within acceptable limits.