Numerical Simulation of N+ Source Pocket PIN-GAA-Tunnel FET: Impact of Interface Trap Charges and Temperature

Abstract

This paper investigates the reliability of PIN-gate-all-around (GAA)-tunnel field-effect transistor (TFET) with N+ source pocket. The reliability of the PNIN-GAA-TFET is examined by analyzing: 1) the impact of interface trap charge (ITC) density and polarity and 2) the temperature affectability on analog/RF performance of the device. It is realized that the interface traps existing at the Si/SiO2 interface modifies the flatband voltage and, thereby, alters the analog and RF characteristics of the device. The analysis is done at various trap charge densities and polarities. The results, thus, obtained reveal that, at higher trap charge density, the device performance alters significantly. It is obtained that, for a donor trap charge density of $3 \times 10^{{12}}$ cm $^{-2}$ , the off-state current of the device degrades tremendously (increases from an order of $10^{-17}$ – $10^{-9}\text{A}$ ). The temperature affectability over the device reveals that, at lower gate bias, the Shockley–Read–Hall phenomenon dominates and degrades the subthreshold current of the device at elevated temperatures. However, for the superthreshold regime, the band-to-band tunneling (BTBT) mechanism dominates. Furthermore, the results show enormous degradation in the off-state current at elevated temperatures, such that, with an increase in the ambient temperature from 200 K to 400 K, the $I_{ \mathrm{\scriptscriptstyle OFF}}$ degrades by an order of $10^{5}$ , i.e., increases from $10^{-18}$ A to $10^{-13}$ A. The results specify that the PNIN-GAA-TFET is insusceptible to the acceptor traps existing at the Si/SiO2 interface in comparison with the donor traps.