Abstract
Accumulation of trap charges at the semiconductor and oxide interface is the most dominating factor and cannot be neglected as it degrades device performance and reliability. This manuscript, presents detailed investigation to analyze the impact of interface trap charges (ITCs) on the performance parameters of the proposed device i.e., heterogeneous dielectric dual metal gate step channel TFET (HD DMG SC-TFET). The comparative study is conducted with dual metal gate step channel TEFT (DMG SC-TFET). The proposed device shows improved current carrying capability, suppressed ambipolar behaviour with steeper subthreshold swing. The purpose of this study to determine the ITCs impact on DC characteristics and analog/RF electrical performance parameters of the proposed device. It further observed that the proposed device exhibit superior performance due to dielectric engineering at oxide layer. Moreover, advanced communication devices must respond linearly therefore, the impact of ITCs on linearity parameters is also studied. From this brief comparative investigation, it is observed that the proposed TFET exhibits negligible distortion in linearity parameters with little or no impact of trap charges as compared to DMG SC-TFET. Thus, proposed TFET is appropriate for ultra-low power high-frequency electronic devices.
Highlights
The semiconductor industry shows rapidly growth in 20th century
Accumulation of trap charges at the semiconductor and oxide interface is the most dominating factor and cannot be neglected as it degrades device performance and reliability. This manuscript, presents detailed investigation to analyze the impact of interface trap charges (ITCs) on the performance parameters of the proposed device i.e., heterogeneous dielectric dual metal gate step channel tunnel field-effect transistor (TFET) (HD DMG SC-TFET)
The impact of ITCs on IMD3 is portrayed in Fig. 16 where it is noticed that proposed TFET shows higher value as compared to DMG SC-TFET
Summary
The semiconductor industry shows rapidly growth in 20th century. The reason behind this is MOSFETs. MOSFETs is scaled down to increase device performance in term of switching speed, power consumption, and package density per unit area constant with reduced fabrication cost This continuous down-scaling of MOSFETs has lead to adverse impact on a device due to unacceptable enhancement in the leakages current that creates major problems at room temperature such as sub threshold leakage current, short circuit effect (SCE), mobility degradation, drain induced barrier lowing (DIBL), impact ionization, hot carrier effects (HCE) and static power consumption [1,2,3]. TFET works on phenomena of quantum tunneling of charge carrier from source to channel which benefits steeper switching characteristics and reduced power consumption [6] Apart from these advantages it suffers from several limitations such as low current driving capability and ambipolar current behavior that degrades the Sachin Kumar, Dharmendra Singh Yadav (a).
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