Interface trap-dependent linearity assessment in single and dual metal gate junctionless accumulation mode (surrounding gate) nanowire MOSFET

Abstract

This paper examines the reliability issue of single metal gate (SMG) and dual metal gate (DMG) junctionless accumulation mode surrounding gate (JAM-SG) MOSFET. The impact of trap charges has also been considered along with the variation of different temperature range (200–400 K). In addition, the analog/RF performance of SMG-JAM-SG and DMG-JAM-SG MOSFET evaluated in terms of the fundamental figure of merits such as ON-state current (ION), OFF-state current (IOFF), ION/IOFF, transconductance (gm), cutoff frequency (fT), current gain, transducer power gain, VIP2, VIP3, IIP3, IMD3 and higher order transconductance parameters gm1, gm2 and gm3. An extensive comparative analysis in terms of overall performance degradation is accomplished between DMG-JAM-SG and SMG-JAM-SG MOSFET using numerical simulation tool (ATLAS 3-D). The temperature sensitivity of device has also been explained with the effect of trap charges. The results reveal that DMG-JAM-SG MOSFET has better immunity contrary to impact of interface trap charges and exhibit high linearity performance, as compared to SMG-JAM-SG MOSFET and DMG-JAM-SG MOSFET is appropriate for highly efficient RFICs and wireless device applications.