Interface trap charge-based reliability assessment of high-k dielectric-modulated nanoscaled FD SOI MOSFET for low power digital ICs: Modeling and simulation

Abstract

This paper proposes the analytical surface potential and threshold-voltage model for performance investigation of gate stack (GS) dual-metal-insulated-gate (DMIG) source-engineered (SE) Fully-depleted silicon-on-insulator (FD SOI) MOSFET for low-power digital applications. In which, a new concept of dielectric-modulated high-k insulator-gap with source engineering has been analytically formulated for the first time in dual-metal-gate technology-based FD SOI MOSFET. The surface potential model is developed using two-dimensional Poisson's equations with including effects of interface trap charges (ITCs) and verified against numerical simulations over the TCAD tool from Silvaco ATLAS™. Also, the parametric analysis has been performed to optimize the device dimensions for better nanoscaled MOS design. Further, a six transistor (6-T) SRAM cell is designed using n/p-GS-DMIG SE FD SOI MOSFET for the analysis of static-noise-margin (SNM). It is observed that the proposed FD SOI MOSFET offers excellent immunity towards short-channel-effects (SCEs) along with improved SRAM circuit performance at different ITC conditions. • Impact of interface Trap Charges (ITCs) on GS-DMIG SE FD SOI MOSFET. • Analytical Modeling of Surface Potential and Threshold Voltage of GS-DMIG SE FD SOI MOSFET. • Analysis of DIBL effect at different ITC Conditions. • Comparative analysis of proposed FD SOI MOSFET in nanoscale regime. • Design and Analysis of 6T-SRAM cell using n-/p-GS-DMIG SE FD SOI with including effects of ITCs.