IC Integration Research Articles

Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si–Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

Impact of Temperature on Structure Deformation for Monolithic Inter-Tier vias In Monolithic 3D IC Packaging System

The approach of monolithic 3D IC (M3D) integration using monolithic inter-tier-vias (MIVs) as interconnect structures is considered. Although, M3D ICs show many benefits of heterogeneous integration without significant area overhead compared to 3D ICs, reliability and thermal issues become daunting challenges to be addressed. Hence, this study focuses on electromigration issues of current density, thermal stress, and structure deformation due to temperature loading. For the analysis Cu and carbon nanotube (CNT) filler materials were chosen in MIV structure. Our analysis reveals that CNT based MIV offers two-fold higher current density and 91% lesser thermal stress compared to Cu based MIVs. Furthermore, at different voltage values, the current density profiles are examined. For the comprehensive investigations of structure deformations, temperature gradient was allowed at the ends of the MIV structure. The results show less deformations in CNT compared to Cu, based on the stress induced among them. The failure time prediction shows higher mean time to failure value of CNT based MIV than Cu based MIV.

Interfacial void ripening in Cu Cu joints

Cu-to-Cu direct bonding technology has been adopted to achieve ultra-high- density interconnects for 3D IC integration. Although the voids in the bonding interface was observed, there was no report on the size distribution and evolution of voids due to ripening. In this paper, we used focused ion beam to prepare specimens for transmission electron microscopy (TEM) study under a specific direction to obtain the plan view images of interface. The voids size distributions under 200 °C for 30, 60 and 120 min were obtained. The interfacial ripening effect was observed. The average void diameter is 49 nm, 70 nm, and 96 nm for the joint annealed for 30, 60, and 120 min, respectively. In addition, the void count within 10 μm2 is 183, 65 and 34 for the three conditions. A simple kinetic model of ripening is developed, and the relationship between radius and annealing time is in good agreement with experimental data.

A solid state process to obtain high mechanical strength in Cu-to-Cu joints by surface creep on (111)-oriented nanotwins Cu

In 3D IC integration, a critical demand of interfacial joints in high-end devices is ultra-fine pitch, below 2 μm. The pitch cannot be fabricated by using solder joints because of its low melting point. Microelectronic industry prefers a solid state process, but the processing temperature cannot be too high, preferable near 250 °C. Thus, Cu-to-Cu direct bonding has attracted much attention. We have bonded the highly (111)-oriented Cu microbumps to highly (111)-oriented Cu films as well as to randomly-oriented Cu films for comparison, at temperatures from 200 to 350 °C. We examined the microstructures of bonded interfaces and conducted shear tests to evaluate the mechanical strength of the Cu joints. The bonded interfaces for the (111) Cu microbumps to (111) Cu films had fewer voids than those bonded to randomly oriented Cu films. In addition, the bonding strength of the latter is much less than the former. We propose that the fast surface diffusivity on the (111) surfaces play a critical role on surface creep, which increases the bonding strength of the Cu joint. A surface creep model and its creep rate are presented, and a comparison to the experimental data has been made; the agreement is reasonable.

(Invited) Crystalline Oxide Semiconductor Applicable to Low-Power Consumption Edge AI

Scaling of Si MOSFETs has proceeded based on scaling law reported by R. H. Dennard in 1974[1], and technologies scaled down to 5 nm node are currently incorporated in ICs in production. Meanwhile, according to an IEEE semiconductor roadmap[2], the 5-nm node device has a gate length of 18 nm, suggesting that scaling is reaching its limit.FETs using crystalline oxide semiconductor (OS), especially, c-axis-aligned crystalline (CAAC)-IGZO, are highly compatible with BEOL process of CMOS because OSFETs can be fabricated at 450°C or lower. Unlike bulk Si, OSFETs can adopt a trench-gate-self-aligned (TGSA) structure[3] enabling isolation from the substrate and accommodating chip bonding technologies. Crystalline oxide semiconductor process contributes to vertical integration required in the future technology.FETs using CAAC-IGZO is preferred to have a charge accumulation structure such as n-i(n-)-n junction (FIG. 1) in which its channel region, especially the region direct below the gate, has to be adjusted to have an i(n-)-type conductivity. Such a junction structure enables threshold voltage control and a reduction in leakage current of the FET. The leakage current of the CAAC-IGZO FET is extremely low, yA (10-24 A)/mm measured at the transistor level at 85°C, which is lower by 10 digits than that of a CMOS device[3].A variety of applications using crystalline OS have been studied, including AI accelerators, high-resolution displays, nonvolatile memories and combination with sensors. Among them, an AI accelerator using crystalline OS has attracted attention[4]. Using crystalline OS enables memory to be placed near compute units. It can also be driven with low current; accordingly, improvement in computational efficiency is expected.Crystalline oxide semiconductor process is a promising technology enabling both high integration and lower power consumption of ICs with CMOS devices. ＜ Reference ＞ [1] R. H. Dennard et al., “Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions,” IEEE Journal of Solid-State Circuits, vol 9, Issue 5, pp.256-268, 1974.[2] International Roadmap for Devices and Systems (IRDS™) 2020 Edition, 2020.[3] H. Kunitake et al., “A c -Axis-Aligned Crystalline In-Ga-Zn Oxide FET With a Gate Length of 21 nm Suitable for Memory Applications,” IEEE J-EDS, vol. 7, pp. 495-502, 2019. Yamazaki et al., “Crystalline IGZO ceramics (crystalline oxide semiconductor)–based devices for artificial intelligence,” Ceramic Engineering & Science, vol. 1, Issue 1, pp.6-20, 2019. [4] D. Saito et al., “IGZO-Based Compute Cell for Analog In-Memory Computing—DTCO Analysis to Enable Ultralow-Power AI at Edge,” IEEE Transactions on Electron Devices, vol. 67, Issue 11, pp.4616-4620, 2020.FIG. 1: Electron holography analysis result of sample using crystalline OS. Figure 1

Demonstration of Low-Temperature Fine-Pitch Cu/SiO₂ Hybrid Bonding by Au Passivation

Fine pitch Cu/SiO2 hybrid bonding has been successfully demonstrated at a low temperature of 120 °C, a breakthrough, using Au passivation method in this work. To explore the bonding mechanism of passivation structures for hybrid bonding in details, Cu-Cu direct bonding with Au passivation on both wafer-level and chip-level has been discussed, including analyses of AFM, SAT, TEM, electrical measurements, and reliability test. Cu/SiO2 hybrid bonding with the fine pitch structure with stable electrical performance can be achieved at low bonding temperature under an atmospheric environment. Accordingly, this Au passivation scheme for Cu/SiO2 hybrid bonding with excellent bonding quality, low thermal budget, and high reliability shows a great feasibility for the 3D IC and heterogenous integration applications.

An extensive survey on future direction for the reduction of noise coupling problem in TSV based 3-dimensional IC integration

Over the period of meticulous scaling IC’s are crucially waiting for a platform which is planar. The most important and actual restriction is nothing, but delay of interconnect is almost approximate to that of devices. To achieve the demands of system performance, new interconnecting materials along with experimental architectures need to be developed. A new integration approach is developed which is nothing but 3D integration technology because this technology is most advantageous and famously used in comparisons to other technologies. Also 3-D technology has a capacity to ensemble with CMOS application because it can easily connect many devices in layers and can be stacked vertically with interconnecting wires having higher thickness among the layers. In this TSV’s plays an important job, which can enable 3-D IC platform. Noise coupling from TSV-to-TSV and TSV-to-Substrate is estimated inside the heterogeneous integration. A vertical TSV pattern is developed to decrease the area per TSV, capacitive coupling and make constructive inductance compared to other design patterns. By developing the vertical TSV patterns in 3D IC the functionality became easier with lesser TSV’s.

Simplifying antenna design through IC integration

Improved IC integration is making it easier to design flat-panel phased array antennas, as Jeff Lane explains

(Invited) Copper Surface Passivation for Low Temperature Cu-to-Cu Bonding Applications

As the IC devices are rapidly scaled down, IC integration has faced several technical bottlenecks: further miniaturization, power delivery and distribution, signal/power integrity, and heat dissipation. In this regard, chip or wafer stacking processes have attracted attention to improve an interconnect delay and an inter-die bandwidth, reduce a form factor, and decrease manufacturing costs. Vertically stacking technology not only enhances device performance, but also can realize heterogeneous packaging systems for the next generation heterogeneous integration. Of the three unit processes in the vertical stacking system, Cu-to-Cu bonding has emerged as a core technology for efficient power density, high bandwidth, and fine-pitch connecton.Various Cu-to-Cu bonding studies have been reported, such as thin metal passivation on Cu surface, self-assembled monolayer that passivates Cu surface with alkane-thiol, surface activated bonding that removes surface oxide layers and contaminants by plasma treatment, and direct bonding interconnect that enables Cu/SiO2 hybrid bonding. Despite many studies, Cu surface oxidation and high bonding temperature are still major issues to be resolved in high volume manufacturing. Sustainable, oxidization-free copper surface prior to Cu-to-Cu bonding is critical, especially since chip-to-chip bonding must still be performed in the air. Therefore, in this study, the copper surface passivation using the two-step plasma treatment has been investigated.The Cu-to-Cu bonding process of less than 300℃ was investigated using the copper nitride passivation. The copper nitride passivation layer was formed on 8-inch Si/SiO2/50nm Ti/1μm Cu using the two-step Ar-N2 plasma treatment process. The purpose of two step plasma treatment is first to remove copper oxides and any contaminants through Ar plasma, activate the Cu surface, and then form a copper nitride layer through N2 plasma. This metastable passivation of couple nanometer thickness prevents further oxidation and reduces surface roughness. In addition, since a copper nitride tends to decompose at 300oC or lower it does not adversely affect Cu bonding interface. The two-step plasma treatment was optimized to improve Cu bonding quality, and optimization was systematically carried out by the response surface methodology (RSM) based on a central composite design (CCD) in design of experiment (DOE). It has been found that copper nitride passivation lasts at lasts for 1 week.. The two-step plasma treatment showed the Cu2O removal and Cu4N formation on the Cu surface. Under the optimized two step Ar-N2 plasma treatment at 300℃, Cu-to-Cu bonding quality has significantly improved compared to the Cu-to-Cu bonding without any surface treatment. The interfacial strength measured by 4-point bending test and shear test and electrical measurements will be discussed.

(Invited) Micro-Transfer-Printing at X-FAB: Demonstration of a New Technology for Wafer-Level Packaging

Introduction Within this publication micro-transfer-printing (µTP) will be introduced as a promising new technology for 3D wafer-level packaging (WLP). The main advantage of µTP arises from the substantial parallel chip transfer from the source wafer to a target device by a visco-elastic stamp. To execute and develop this versatile technology a pilot line has been installed in the X-FAB MEMS Foundry GmbH clean room facilities within a funded EU project (MICROPRINCE). To demonstrate the general process capabilities recent results on the preparation and integration of silicon-based ICs, optical filters and III/V semiconductors shall be discussed. Contents The general principle of µTP is based on the utilization of an elastomer stamp to transfer devices or arrays of devices from their native substrate (source) to a non-native target material [1]. A mandatory requirement for this transfer is that the stamp, typically made of polydimethylsiloxane (PDMS), provides tunable adhesion properties to the printable chiplet [2]. Thereby, high adhesion during the “pick-up” as well as low adhesion forces during the “placing” steps can be achieved.The general process flow for micro-transfer-printing is illustrated in Figure 1 .Therein, the main advantage of µTP, namely the extensive parallelization of the chip placement (schematics a.-e.), can be recognized. Such a parallelization offers the possibility of a major process time reduction.Prior to the transfer operation, the source wafer has to be prepared for the printing process. This involves the formation of reliable anchor and tether structures which carry the printable chiplets after the release etch. Another crucial requirement on these structures is that they provide a controlled micro-fracture and release the transfer chiplets to the stamp [3]. An example of a print-ready optical filter device is furthermore illustrated in Figure 1g.The target on the other hand has to be coated with an adhesion providing polymer (see red layer in Figure 1d.-f.) for which bisbenzocyclobutene (BCB) is applied at X-FAB.After the printing itself, a post-processing comprising the patterning of applied adhesion media, a wiring via a Cu redistribution layer (RDL) and a passivation is required to allow the functionality of active devices (see Figure 1f.). Figure 1h shows two 3D-integrated demonstrator devices which have been printed on a XL035 technology from X-FAB and which were afterwards connected via a Cu-RDL layer. Within the printing experiments of these chiplets a print yield of about 99.9% with a placement accuracy of down to 3σ ≤ 0.78µm has been achieved. Conclusions By this publication the Micro-transfer-printing (µTP) technology and its technical implementation will be introduced. To build up and develop µTP processes a pilot line has been installed in the X-FAB MEMS Foundry GmbH via a funded ECSEL project called “MICROPRINCE”. To execute the µTP technology for 3D integration several process steps have to be executed to prepare a source wafer for the printing operation, transfer the chiplets to a non-native target and connect them afterwards during the prost-processing. The process sequence itself will be explain in more detail within the presentation on examples of optical filters, silicon ASICs as well as III/V semiconductor chiplets. Acknowledgements This work is funded by ECSEL JU under grant agreement No 737465 and by the BMBF No ESECS16204. Further, the authors like to thank all X-FAB internal and external MICROPRINCE partners for their support.

Thermal management in TSV based 3D IC Integration: A survey

Three Dimensional IC (3D IC) integration is one of the emerging technology which suits CMOS applications by stacking various IC layers vertically. In 3D IC, IC Layers are interconnected electrically using Through Silicon Vias (TSV’s) and mechanically by Cu–Cu bonding. The major drawbacks in 3D IC structures are thermal issues between layers and noise coupling between TSV-to-substrate and TSV-to-TSV which leads significantly on the overall system performance. This paper presents an extensive survey on one of the major issue in 3D based IC integration technique called thermal issues between the layers and how the researchers have tried to overcome the problems by introducing various materials which are suitable for elimination of hotspot, by introducing spreaders among the layers. This extensive survey work shows the complete roadmap for the thermal management in future IC Integration.

FPGA Implementation of Memory Bists using Single Interface

The development of IC integration technologies leads to an extensive use of memories and buffers in different memory intensive applications. Therefore, probability of occurrence of fault in every single read and writes operation is increased in Memory BIST (MBIST). There were many testing approaches that were developed for efficient testing and diagnosis of fault. However, all algorithms are not strengthened enough to detect all possible faults that may be present due to fabrication errors or environmental disturbance. Keeping this in mind and taking the possibility of development of efficient algorithm a hybrid memory testing algorithm is presented. To overcome those drawbacks, pipelining based MBIST designed to detect the all the types of memory faults by utilizing March-C testing algorithm. By introducing the Pipelining approach, majorly path delays are reducing. The proposed architecture designed and verified using Xilinx ISE environment under various testing methods with respect to the different category of memories. The simulation and synthesis results shows that the proposed method shows the enhanced performance with the hardware resource utilization and delay consumption compared to the conventional approaches.

Performance evaluation of noise coupling on Germanium based TSV filled material for future IC integration technique

• Due to its CTE mismatch and Electromigration (EM) issues of Cu as TSV, Germanium can be used as an alternative material. • Quantum-well (QW) formed between Silicon substrate and Germanium core can be used as a high-speed TSV interconnect. • It opens up the window towards the future IC Integration (3D IC). 3D IC Integration shows the most emerging technology for future integration nodes which is now a most important trend for the semiconductor industries. Through-silicon-via (TSV) based integration is the prime technique to facilitate 3D IC integration without compromising the Moore’s law. It is likely to usher the IC industries a paradigm shift from planar integration as it provides major benefits like improvement of system performance, power and enables heterogeneous integration. In this paper, we report Germanium/poly-germanium as an substitute material for Silicon/poly-silicon due to its superior carrier mobility. Mobility of electrons and holes in c-Silicon is 1500 cm 2 /V-s and 450 cm 2 /V-s respectively, where as in c-Germanium, the respective values are 3900 cm 2 /V-s and 1900 cm 2 /V-s. Therefore, considering these carrier mobility values we can envisage that poly germanium will be one of the ideal candidate towards realizing a high speed TSV interconnect when compared with poly-silicon. Nevertheless, even though copper is used widely to fill TSVs, it is also bereft of proper thermal expansion match with Silicon/dielectric (SiO 2 ). The coefficient of thermal expansion (CTE) of Cu (∼17.5x 10 -6 /°C) is many times more than of silicon (∼2.5x 10 -6 /°C). Hence, there will be heavy mismatch between Cu filled TSV and Silicon/SiO 2 , and then it creates stress and strain between the interfaces. The CTE of germanium (5.8x 10–6/°C) is very close to Silicon, thus there CTE mismatch is very less, this fact is also an added advantage for Germanium to challenge copper as TSV material.

An extensive survey on reduction of noise coupling in TSV based 3D IC integration

3D Integration technology is probably the best methodologies among others which suits CMOS applications with in various layers of devices are stacked with high thickness interconnects between the layers. In 3D IC structure electrical and thermal models are introduced for the interface between Through-Silicon-Via’s (TSV’s). TSV’s can be used to enable the 3-D platform; however this TSV’s will represent additional concerns. TSV-to-substrate and TSV-to-TSV noise coupling is assessed inside the 3-D IC’s. A vertical TSV’s design is proposed to reduce the area per TSV, capacitive coupling and effective inductance as compared with the other classical design patterns. TSV’s and substrate noise coupling is one of the major drawbacks in 3D IC. Some of the researchers have tried to overcome the problems in TSV based 3D IC due to noise coupling using different models, materials and different circuit techniques. This paper shows the complete road map for the noise coupling reduction in future IC integration.

Simplistic approach to reduce thermal issues in 3D IC integration technology

Abstract A practical exhibition of the consequences of the 3D IC in heat management by adding the fin and heat spreaders to thermal through silicon via (TTSV) and IC respectively is proposed in this paper. Thermal cooling and its distribution of burnt potentials at various conditions are the different possessions which can be simulated using FEM simulator. This paper illustrate materials like Silicon nitride (Si3N4), Aluminium oxide (Al2O3), Silicon dioxide (SiO2) as they have the high thermal conductivity and high temperature capabilities which leads to the thermal management in the 3D IC design. Currently, semiconductor industries has cognizance of the metrics such as low density, high thermal strength, good facture of toughness, excellent wear resistance of Silicon nitride and it also shows better capabilities of high temperature, oxidation resistance and high retention strength compared to other metals. Besides silicon nitride has good resistance to thermal shock due to low coefficient of thermal expansion. Aluminium oxide is known for an better electrical insulator but has high thermal conductivity and which can be utilized as the substrate for integrated circuits. The high temperature furnace insulations and electrical insulations are designed by using the aluminium oxides as it has high boiling points and melting points. This makes the rapid use of alumina films in manufacture of IC industry. The other uses of alumina films include spark plug insulators, micro-electric substrates and insulating heat sinks. Silicon dioxide has the properties which helps to use them as the insulator material in IC technology as it has high thermal stability and making it useful for device integration and has high dielectric strength and thermal expansion coefficient is very low and in this paper we have taken these three materials and these materials have been implemented in our model and advertence the outcomes that which material is working efficiently and preciously.

Design of a Tri-Axial Surface Micromachined MEMS Vibrating Gyroscope.

Gyroscopes are one of the next killer applications for the MEMS (Micro-Electro-Mechanical-Systems) sensors industry. Many mature applications have already been developed and produced in limited volumes for the automotive, consumer, industrial, medical, and military markets. Plenty of high-volume applications, over 100 million per year, have been calling for low-cost gyroscopes. Bulk silicon is a promising candidate for low-cost gyroscopes due to its large scale availability and maturity of its manufacturing industry. Nevertheless, it is not suitable for a real monolithic IC integration and requires a dedicated packaging. New designs are supposed to eliminate the need for magnets and metal case package, and allow for a real monolithic MEMS-IC (Integrated Circuit) electronic system. In addition, a drastic cost reduction could be achieved by utilizing off-the-shelf plastic packaging with lead frames for the final assembly. The present paper puts forward the design of a novel tri-axial gyroscope based on rotating comb-drives acting as both capacitive sensors and actuators. The comb-drives are comprised of a single monolithic moving component (rotor) and fixed parts (stators). The former is made out of different concentrated masses connected by curved silicon beams in order to decouple the motion signals. The sensor was devised to be fabricated through the PolyMUMPs® process and it is intended for working in air in order to semplify the MEMS-IC monolithic integration.

Noise performance improvement in 3D IC integration utilizing different dielectric materials

Semiconductor Industries are mainly facing problems by using planar integration (2D IC) in order to overcome the paradigm shift has been adopted as vertical IC integration so called 3D IC. It not only provides higher bandwidth, higher system performance, but also consumes less power with system scaling. 3D IC has an ability to coordinate IC chips by stacking them vertically and electrically associated utilizing TSV's (Through Silicon Via). By utilizing TSV's in 3D IC, TSV noise coupling is one of the vital factors for the system performance aspects. TSV's play major role in carrying the electrical signal between the IC’s of 3D integrated structures. Noise coupling is the major drawback between the signal carrying TSV’s (ETSV) and victim TSV’s. In this work, we have shown better electrical integrity by reducing the noise coupling from TSV to Silicon substrate by essentially changing the CMOS compatible dielectric materials as liner structures. In addition to this performance of various proposed structures are analyzed and verified under different parameters like electrical signal and at high frequencies. Also, the noise coupling analysis has been studied for Electrical TSV’s (ETSV), TTSV (Thermal Through Silicon Via) and heat source. Finally, our work shows liner material Teflon AF1600 shows comparably better noise coupling performance for all the proposed models even at higher frequencies like THz.

Simplistic approach to alleviate noise coupling issues in 3D IC integration

Through-silicon-via (TSV) technology has emerged as the key technology to enable 3D IC integration. 3D integration is seen as the leading candidate, which can help in sustaining Moore’s Law to future IC technology nodes. It clearly set a benchmark to the IC industry due to its tremendous benefits in performance, data bandwidth, and supports heterogeneous integration. In 3D IC structure TSV’s are used to carry the overall electrical signal between the layers. The major drawback in the TSV based 3D integration is noise coupling between aggressive (electrical signal carrying TSV; ETSV) and victim TSV’s (ground). It can be reduced by creating very good isolation between TSV’s and Si substrate by using different liner materials around TSV’s. In this work, we have addressed various TSV models to reduce noise coupling between the TSV’s. The models we have studied are single layer model and stacked layers of liner model. Apart from this we have studied how the core materials in the TSV reduces noise coupling between aggressive and victim TSV’s. Also, we have shown the high frequency study for proposed models. Finally, our work shows single layer model with Crystalline-Germanium is comparably better noise coupling reduction even at higher frequency.

Noise Performance Improvement In Future IC Integration using Perylene-N As Dielectric Material

Ever-growing consumer demand for smaller and faster devices opens up to think the semiconductor industries about another direction of improvement during IC integration as long run metal wires not only reduces the form factor of the system but also decreases the system performance by creating RC delay which in turn reduces the bandwidth during communication. In order to improve the system performance the devices must be interconnected vertically known as 3D IC integration. In this emerging technique, different modules are mounted on different layers with Si substrate and these layers are placed one on other. TSV’s (Through Silicon Via or Through Substrate Via) are the basic building blocks of the 3D ICs which are playing an important role to create high performance electrical path between thin IC chips. TSV’s carries the entire electrical signal between the layers of 3D structure. Major drawback is poor electrical signaling due to the noise coupling between signal carrying TSV’s(aggressive TSV’s) and ground TSV’s(victim TSV’s).Therefore there is a strong need of isolation between Si substrate and TSV’s with proper liner materials and structures. Perylene-N is one of the most promising dielectric material for less area consumption and less power consumption. In this paper, we compared the results for Perylene-N and conventional SiO2 liner for ETSV’s. The performance of this structure is analyzed and verified under different parameters to reduce the noise coupling. In this structure dielectric-metal-dielectric are arranged around the Copper TSV. The achieved result shows that more noise coupling is reduced by using Perylene-N as dielectric material as compared with conventional SiO2. Furthermore, Perylene-N shows 33 dB improvements in noise coupling performance at THz frequencies which is verified and validated as well in this work.

Noise Performance Improvement in Future IC Integration using Perylene-N as Dielectric Material

Ever-growing consumer demand for smaller and faster devices opens up to think the semiconductor industries about another direction of improvement during IC integration as long run metal wires not only reduces the form factor of the system but also decreases the system performance by creating RC delay which in turn reduces the bandwidth during communication. In order to improve the system performance the devices must be interconnected vertically known as 3D IC integration. In this emerging technique, different modules are mounted on different layers with Si substrate and these layers are placed one on other. TSV’s (Through Silicon Via or Through Substrate Via) are the basic building blocks of the 3D ICs which are playing an important role to create high performance electrical path between thin IC chips. TSV’s carries the entire electrical signal between the layers of 3D structure. Major drawback is poor electrical signaling due to the noise coupling between signal carrying TSV’s(aggressive TSV’s) and ground TSV’s(victim TSV’s).Therefore there is a strong need of isolation between Si substrate and TSV’s with proper liner materials and structures. Perylene-N is one of the most promising dielectric material for less area consumption and less power consumption. In this paper, we compared the results for Perylene-N and conventional SiO2 liner for ETSV’s. The performance of this structure is analyzed and verified under different parameters to reduce the noise coupling. In this structure dielectric-metal-dielectric are arranged around the Copper TSV. The achieved result shows that more noise coupling is reduced by using Perylene-N as dielectric material as compared with conventional SiO2. Furthermore, Perylene-N shows 33 dB improvements in noise coupling performance at THz frequencies which is verified and validated as well in this work.