Simplistic approach to alleviate noise coupling issues in 3D IC integration

Abstract

Through-silicon-via (TSV) technology has emerged as the key technology to enable 3D IC integration. 3D integration is seen as the leading candidate, which can help in sustaining Moore’s Law to future IC technology nodes. It clearly set a benchmark to the IC industry due to its tremendous benefits in performance, data bandwidth, and supports heterogeneous integration. In 3D IC structure TSV’s are used to carry the overall electrical signal between the layers. The major drawback in the TSV based 3D integration is noise coupling between aggressive (electrical signal carrying TSV; ETSV) and victim TSV’s (ground). It can be reduced by creating very good isolation between TSV’s and Si substrate by using different liner materials around TSV’s. In this work, we have addressed various TSV models to reduce noise coupling between the TSV’s. The models we have studied are single layer model and stacked layers of liner model. Apart from this we have studied how the core materials in the TSV reduces noise coupling between aggressive and victim TSV’s. Also, we have shown the high frequency study for proposed models. Finally, our work shows single layer model with Crystalline-Germanium is comparably better noise coupling reduction even at higher frequency.