High Drain Voltage Research Articles

Asymmetric Split-Gate 4H-SiC MOSFET with Embedded Schottky Barrier Diode for High-Frequency Applications

4H-SiC Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) with embedded Schottky barrier diodes are widely known to improve switching energy loss by reducing reverse recovery characteristics. However, it weakens the static characteristics such as specific on-resistance and breakdown voltage. To solve this problem, in this paper, an Asymmetric 4H-SiC Split Gate MOSFET with embedded Schottky barrier diode (ASG-MOSFET) is proposed and analyzed by conducting a numerical TCAD simulation. Due to the asymmetric structure of ASG-MOSFET, it has a relatively narrow junction field-effect transistor width. Therefore, despite using the split gate structure, it effectively protects the gate oxide by dispersing the high drain voltage. The Schottky barrier diode (SBD) is also embedded next to the gate and above the Junction Field Effect transistor (JFET) region. Accordingly, since the SBD and the MOSFET share a current path, the embedded SBD does not increase in RON,SP of MOSFET. Therefore, ASG-MOSFET improves both static and switching characteristics at the same time. As a result, compared to the conventional 4H-SiC MOSFET with embedded SBD, Baliga′s Figure of Merit is improved by 17%, and the total energy loss is reduced by 30.5%, respectively.

Electrical instability in short channel organic thin-film transistors induced by lucky-polaron mechanism

In this work we study the electrical stability under both gate bias stress and gate and drain bias stress of short channel (L = 5 μm) bottom contact/top gate OTFTs made on flexible substrate with solution-processed organic semiconductor and fluoropolymer gate dielectric. These devices show high field-effect mobility (μ FE > 1 cm 2 V −1 s −1 ) and excellent stability under gate bias stress (bias stress V ds = 0V). However, after prolonged bias stress performed at high drain voltage, V ds , the transfer characteristics show a decreased threshold voltage, degradation of the subthreshold slope and an apparent increase in the field effect mobility. Furthermore, the output characteristics show an asymmetry when measured in forward and reverse mode. These experimental results can be explained considering that the bias stress induces the damage of a small part of the device channel, localized close to the source contact. The analysis of the experimental data through 2D numerical simulations supports this explanation showing that the electrical characteristics after bias stress at high V ds can be reproduced considering the creation of donor-like interface states and trapping of positive charge into the gate dielectric at the source end of the device channel. In order to explain this degradation mechanism, we suggest a new physical model that, assuming holes injection from the source contact into the channel in bounded polarons, envisages the defect creation at the interface near the source end of the channel induced by injection of holes that gained energy from both the high longitudinal electric fields and the polaron dissolution. • Bias stress induced instability in short channel OTFTs is due to small defected channel region at the source contact. • Interface states and charge trapping into the gate dielectric at the source end have been considered in 2D simulations. • A “Lucky-polaron” mechanism well explains the creation of a defected region and carrier injection into the gate dielectric.

(Invited) Fabrication of Ge-on-Insulator By Epitaxial Growth and Ion-Implanted Exfoliation for Electronics and Optoelectronics Applications

1. IntroductionGe has been received much interest as a CMOS channel material and a near-infrared optical material due to its superior characteristics [1,2]. For application use, Ge-on-Insulator (GOI) structure is necessary to suppress large leakage current originated from the narrow bandgap. A method combined wafer bonding and layer splitting by hydrogen ion (H+) implantation, known as Smart-CutTM and realized for Si-on-Insulator fabrication, has been tried to apply for GOI with large diameter, uniform thickness, and single crystal [3-5]. In this study, we fabricated GOI by Smart-CutTM technique and demonstrated electronic and optoelectronic devices on the GOI. Besides, we combined the epitaxial growth method to improve the quality of GOI.2. Experimental, Results, and DiscussionsGOI fabrication procedure by conventional Smar-CutTM method is shown in Fig. 1 [5]. H+ implantation with the dose of 4×1016 cm-2 and energy of 120 keV into Ge was performed through 100 nm-thick SiO2. After SiO2 removal, 3 nm-Al2O3 and 50 nm-SiO2 were formed on the Ge and Si substrates, respectively. Then, the Al2O3/Ge and the SiO2/Si were manually bonded. After annealing in N2 ambient at 300 °C to enhance bonding strength [6], layer splitting was carried out by annealing at 400 °C. GOI thinning by wet etching and surface flatten by chemical mechanical polishing (CMP) were performed. We fabricated both p- and n-MOSFETs with metal source/drain (S/D) on the GOI. The p-MOSFET is an accumulation mode device with ohmic PtGe/Ge S/D. On the other hand, n-MOSFET is an inversion mode device with rectifying TiN/Ge S/D. Both devices work successfully as shown in Fig. 2. We also demonstrate asymmetric metal/Ge/metal photodiode on the GOI. PtGe and TiN are also used as electrodes for hole and electron injection, respectively. Figure 3 shows electroluminescence (EL) spectra for the photodiodes fabricated on the GOI and the bulk Ge. The GOI device shows higher EL intensity than that of bulk Ge. It is considered carrier confinement effect by thin Ge crystal.However, the MOSFETs show a large leakage current at the high drain voltage region. Also, the photodiode on GOI has a broader spectra peak. Figure 4 is the cross-sectional TEM image of the GOI before GOI thinning. There are many defects as black dots near both the split surface and the buried oxide (BOX) interface. The defects near the BOX are serious because this region will be kept after GOI thinning, and cause the degradation of device characteristics (leakage current and broad PL peak). They may be introduced by H+ implantation.To avoid the introduction of the defect during GOI fabrication, we propose an alternative method which is epitaxial growth of a new Ge layer on H+ implanted surface, as shown in Fig. 5. In this method, all defective layer was removed after layer splitting and only epi-Ge layer remains on the handle Si. Figure 5 also shows electron concentrations and mobilities of the GOIs evaluated by Hall effect. The conduction type of the GOI by conventional Smart-CutTM changes from n-type to p-type due to defect introduction. On the other hand, the proposed method successfully keeps the original conduction type (n-type). Although electrical characteristics should be improved more, it is clarified that defect elimination before bonding is important for GOI fabrication by Smart-CutTM.3. ConclusionWe fabricated GOI by Smart-CutTM and demonstrated MOSFETs and photodiode on the GOI. Although both devices successfully work, TEM analysis clarified there are lots of defects near the GOI/BOX interface. Alternative way combined epitaxial growth to eliminate the defects succeeded to improve the electrical characteristics of the GOI.AcknowledgmentThis work is supported by JSPS KAKENHI (No. 19K15028 and 19H05616) and the Research Institute of Electrical Communication, Tohoku University.

Characterization of Threshold Voltage Instability Under Off-State Drain Stress and Its Impact on p-GaN HEMT Performance

The p-GaN gate technology is commonly implemented to achieve normally OFF gallium nitride (GaN) devices. Nonetheless, the threshold voltage instability under OFF-state stress remains a concern. In this article, the characterization technique of threshold voltage shift is proposed and the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift's impact on device performance is investigated. Specifically, a fast V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> the measurement circuit is introduced and validated to successfully characterize both the magnitude and the time-constant of the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift. According to the experimental results, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> increases by more than 50% within several μs after the high drain voltage is applied. In contrast, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> slowly (tens of seconds) gets back to the static value after the stress is removed. Following the characterization, the threshold voltage instability's impact on the device's static/switching performance is studied experimentally. A knee point shift is observed at low gate voltage, and the static ON-resistance value remains unchanged. Regarding the switching performance, the turn-ON loss increases by >20% after the high drain voltage stress. The change in turn-ON loss can be reduced when the gate resistance is decreased from 20 to 0 Ω. In terms of the turn-OFF loss, the impact of the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> shift is negligible. It is concluded that time-dependent threshold voltage shift needs to be considered in p-GaN device's modeling, and high gate drive voltage together with low gate resistance is recommended to mitigate the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> instability's effect on p-GaN high-electron-mobility transistor's performance.

Multilayer SiNx passivated Al2O3 gate dielectric featuring a robust interface for ultralong-lifetime AlGaN/GaN HEMT

This paper presents a multilayer SiNx passivation-based robust and high-reliability interface for effective suppression of current collapse effect and reduction of leakage current at AlGaN/GaN heterostructure. The performance characterization of the fabricated HEMT reveals a high drain saturation current, peak extrinsic transconductance (up to 199.5 mS/mm), and dynamic RON/static RON of 1.067 even at a high drain voltage of 700 V. Moreover, an excellent mean time-to-failure of 2.204 × 108 h at an activation energy of 2.621 eV at TC = 150 °C is obtained, which indicates that the developed HEMT exhibits an ultralong operation lifetime for RF power applications.

3.3-kV 4H-SiC Split-Gate DMOSFET with Floating p+ Polysilicon for High-Frequency Applications

A split-gate metal–oxide–semiconductor field-effect transistor (SG-DMOSFET) is a well-known structure used for reducing the gate–drain capacitance (CGD) to improve switching characteristics. However, SG-DMOSFETs have problems such as the degradation of static characteristics and a high gate-oxide electric field. To solve these problems, we developed a SG-DMOSFET with floating p+ polysilicon (FPS-DMOSFET) and compared it with a conventional planar DMOSFET (C-DMOSFET) and a SG-DMOSFET through Technology Computer-Aided Design (TCAD) simulations. In the FPS-DMOSFET, floating p+ polysilicon (FPS) is inserted between the active gates to disperse the high drain voltage in the off state and form an accumulation layer over the entire junction field effect transistor (JFET) region, similar to a C-DMOSFET, in the on state. Therefore, the FPS-DMOSFET can minimize the degradation of static characteristics such as the breakdown voltage (BV) and specific on resistance (RON,SP) in the split-gate structure. Consequently, the FPS-DMOSFET can shorten the active gate length and achieve a gate-to-drain capacitance (CGD) that is less than those of the C-DMOSFET and SG-DMOSFET by 48% and 41%, respectively. Moreover, the high-frequency figure of merit (HF-FOM = RON,SP × CGD) of the FPS-DMOSFET is lower than those of the C-DMOSFET and SG-DMOSFET by 61% and 49%, respectively. In addition, the FPS-DMOSFET shows an EMOX of 2.1 MV/cm, which guarantees a gate oxide reliability limit of 3 MV/cm. Therefore, the proposed FPS-DMOSFET is the most appropriate device to be used in high-voltage and high-frequency electronic applications.

Reducing the Drain Leakage Current in a Double-Gate Junctionless MOSFET Using the Electron Screening Effect

This study investigated the position of electrons and holes in the ON and OFF states of double-gate junctionless transistors, and then three structures were proposed to create an electron-filled region exposing the drain-side inside the channel to the electron screening effect. Formation of an electron cloud in the channel and on the drain-side damps the electric field resulting from the drain voltage as the electric field passes through the electron cloud before reaching the main channel. Accordingly, in the structure with a drain-side gate, with the electric field decay introduced by the drain to the main channel, the carrier density increased compared to other structures, eventually reducing drain leakage current and improving the channel length modulation (CLM), threshold voltage, drain induced barrier lowering effect, and subthreshold slope in this structure. In the N+ pocket structure, despite the decrease in the electric field resulting from the drain voltage, the drain leakage current and the CLM were increased. In the N+ SiGe pocket structure, although the electric field resulting from the drain voltage along the channel length was reduced compared to the main structure, the drain leakage current and CLM experienced an increase. Moreover, the results showed that at low drain voltages, the drain leakage current in the N+ pocket structure was higher than that of the N+ SiGe pocket, but at high drain voltages, the order was reversed.

P‐1.5: High‐Voltage characteristics of Top‐Gate Amorphous InGaZnO Thin‐Film Transistors

In this paper, we investigated high‐voltage characteristics of topgate amorphous InGaZnO thin‐film transistors. Results indicate that the saturation current decreases at high drain bias. Moreover, the threshold voltage (Vth) positive shift after device biased at the high drain voltage and the shift magnitude become larger at shorter channel length devices. These observations are attributed to the fact that hot electrons were produced due to the strong drain to source electric field and trapped in the gate insulator. The device performance was recovered after 1000‐s negative gate bias at 60 °C.

Metal-Contact Improvement in a Multilayer WSe2 Transistor through Strong Hot Carrier Injection.

Hot carrier injection (HCI), occurring when the horizontal electric field is strongly applied, usually affects the degradation of nanoelectronic devices. In addition, metal contacts play a significant role in nanoelectronic devices. In this study, Schottky contacts in multilayer tungsten diselenide (WSe2) field-effect transistors (FETs) by hot carrier injection (HCI), occurring when a high drain voltage is applied, is investigated. A small number of hot carriers with high energy reduces the Schottky barrier height and improves the performance of FETs effectively rather than damaging the channel. Thermal annealing at the end of the fabrication process increases device performance by causing interfacial reactions of the source/drain electrodes. HCI causes a significant enhancement in the local asymmetry, especially in the subthreshold region. The subthreshold swing (SS) of the thermally annealed FETs is significantly improved from 9.66 to 0.562 V dec-1 through the energy of HCI generated by a strong horizontal electric field. In addition, the contact resistances (RSD), also called series resistances, extracted by a four-probe measurement and a Y-function method were also improved by decreasing to a 10th through the energy of HCI. To understand the asymmetrical characteristics of the channel after the stress, we performed electrical analysis, electrostatic force microscopy (EFM), and Raman spectroscopy.

No-Snapback LDMOS Using Adaptive RESURF and Hybrid Source for Ideal SOA

A simple modification to the lateral DMOS is demonstrated, enabling a significant extension to the electrical safe operating region. This approach uses a novel Hybrid Source to suppress the parasitic bipolar, prevent snapback and enable operation at high drain voltage & current regions that have traditionally been inaccessible due to triggering of the parasitic bipolar. Trigger currents exceeding 10x that of conventional PN source devices under grounded gate, very fast TLP conditions have been achieved. This improvement does not compromise the basic DC parameters, such as specific on-resistance or breakdown voltage. This paper covers the device architecture, formation of the Hybrid Source, electrical performance, TCAD simulation and discussion of the mechanisms behind this new device and the improvements it enables.

Analysis of Low Voltage RF Power Capability on AlGaN/GaN and InAlN/GaN HEMTs for Terminal Applications

In this work, low voltage RF power capability on AlGaN/GaN and InAlN/GaN HEMTs is analyzed from the perspective of DC and pulse characteristics, for terminal applications whose operating voltage is usually in the range of 3 to 15 V. Device fabrication is performed on mature AlGaN/GaN heterojunction as well as strongly polarized InAlN/GaN heterojunction, to make a comparison of low voltage RF power capability between two devices. Although it suffers from relatively severe RF dispersion, InAlN/GaN HEMT delivers higher output power density (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) than its opponent, benefiting from the lower parasitic resistance and knee voltage as well as higher output current density. At 8 GHz, P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> of 1.62 W/mm and 1.10 W/mm are achieved for InAlN/GaN and AlGaN/GaN HEMT, respectively, both of which are biased at class AB operation and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> of 9 V. However, the tremendous degradation of power added efficiency (PAE) occurs as the higher drain voltage is applied on InAlN/GaN HEMT, as the result of the severe gate leakage. What is more, a higher PAE is more necessary than P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> for terminal applications. Either InAlN/GaN HEMT or AlGaN/GaN HEMT has its own specific voltage range to deliver higher PAE. Concretely, InAlN/GaN HEMT is more suitable to applications with operating voltage not exceeding 6 V, and AlGaN/GaN HEMT is preferred for ones with relatively higher voltage, accompanied by the decent PAE as high as 62% to 66% and moderate P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> to meet the demand of various low voltage terminal applications.

Secondary Effects in Electrical Behavior of Body-Diode Integrated AlGaN/GaN HEMTS

We have recently demonstrated dual-gate control in AlGaN/GaN high electron mobility transistors (HEMTs) with the integration of body-diode based back-gate [1]. To integrate body-diode, conventional AlGaN/GaN HEMT structure is grown on a p-GaN layer and a back-gate terminal is connected to the underlying p-GaN layer. This design allows the back-gate voltage to control the depletion width of the body-diode, which in turn modulates the two-dimensional electron gas (2DEG) density at the AlGaN/GaN interface. A positive/negative shift in the threshold voltage is obtained by increasing/decreasing the depletion width of the body-diode with the application of back-gate voltage. With dual gate control, we have successfully demonstrated shift in the threshold voltage of a normally-ON HEMT towards normally-OFF mode along with improved breakdown voltage. Here we present, observations of secondary effects in the integrated body-diode AlGaN/GaN HEMT device structure. Secondary effects are investigated under both biased and floating back-gate conditions [2]. Our results show that, at higher drain voltages, bias at the drain terminal plays a crucial role in biasing the body-diode under dynamic operation. Secondary effects such as kink-effect in the saturation channel current and light emission under the source terminal are observed under dynamic operation. We will further discuss the effect of parasitic bipolar junction transistor (BJT) formation on the device performance in this integrated device configuration.

Analysis on degradation mechanisms of normally-off p-GaN gate AlGaN/GaN high-electron mobility transistor* *Project supported by the Equipment Developing Advanced Research Program of China (Grant No. 6140A24030107).

The degradation mechanisms of enhancement-mode p-GaN gate AlGaN/GaN high-electron mobility transistor was analyzed extensively, by means of drain voltage stress and gate bias stress. The results indicate that: (i) High constant drain voltage stress has only a negligible impact on the device electrical parameters, with a slightly first increase and then decrease in output current; (ii) A negative shift of threshold voltage and increased output current were observed in the device subjected to forward gate bias stress, which is mainly ascribed to the hole-trapping induced by high electric field across the p-GaN/AlGaN interface; (iii) The analyzed device showed an excellent behavior at reverse gate bias stress, with almost unaltered threshold voltage, output current, and gate leakage current, exhibiting a large gate swing in the negative direction. The results are meaningful and valuable in directing the process optimization towards a high voltage and high reliable enhanced AlGaN/GaN high-electron mobility transistor.

The role of SiN/GaN cap interface charge and GaN cap layer to achieve enhancement mode GaN MIS-HEMT operation

The thickness increase of gallium nitride (GaN) cap layer from 2 nm to 35 nm to achieve an enhancement mode GaN MIS-HEMT (Metal-Insulator-Semiconductor High-Electron-Mobility Transistor) with a threshold voltage (Vth) of +0.5 V is studied using TCAD simulations. The simulations are calibrated to measured I-V characteristics of the 1 μm gate length GaN MIS-HEMT with the 2 nm thick GaN cap. A good agreement at low and high drain voltages (VDS=1 V and 5 V) between simulations and measurements is achieved by using a quantum-corrected drift-diffusion transport model. The enhancement mode GaN MIS-HEMT with a GaN cap thickness of 35 nm achieves Vth = + 0.5 V thanks to positive interface traps occurring between the SiN passivation layer and the GaN cap as reported experimentally. The simulations indicate that a parasitic channel is created at the interface between the SiN layer and the 35 nm GaN cap. Our study also shows an increase in the breakdown voltage from 100 V to 870 V when a thickness of the GaN cap layer increases from 15 nm to 35 nm.

Drain-Voltage-Induced Secondary Effects in AlGaN/GaN HEMTs With Integrated Body-Diode

Integration of body-diode-based back-gate control in AlGaN/GaN high-electron mobility transistors (HEMTs) was recently demonstrated by the authors to enable dynamic control of the device characteristics. Here, we present an experimental study of drain-voltage-induced secondary effects in AlGaN/GaN HEMTs with integrated body-diode. Both the three-terminal and four-terminal device characteristics are studied to understand the secondary effects in this configuration. The results show that the voltage at the drain terminal plays a crucial role in biasing the body-diode under dynamic operation. Drain-voltage-induced dynamic biasing of the body-diode is observed both under the biased and floating back-gate conditions. The kink-effect in the saturation channel current and light emission at the source terminal are observed at higher drain voltages. Our results show that a combination of high resistivity of the p-GaN layer and the direct bandgap nature of III-nitride (III-N) material prevents the parasitic bipolar junction transistor (BJT)-triggered latch-up mechanism in this device structure.

전산모사 시뮬레이션을 이용한 Laterally Diffused MOS(LDMOS)에서의 Displacement Defect의 영향

The effect of displacement defect due to radiation effect is investigated in laterally diffused metal oxide semiconductor (LDMOS) using technology computer-aided design (TCAD) simulation. The displacement defect with acceptor-like trap of deep level (Ec-0.4eV) under shallow trench isolation (STI) induces the worst degradation of Id-Vg characteristic. The location of defect under STI with lightly doping concentration is the worst position to transfer characteristic of Id-Vg. For breakdown voltage characteristic, the positions and types of displacement trap are negligible, because of high drain voltage operation.

CMOS Active Gate Driver for Closed-Loop dv/dt Control of GaN Transistors

This article shows both theoretical and experimental analyses of a fully integrated CMOS active gate driver (AGD) developed to control the high dv/dt of GaN transistors for both 48 and 400 V applications. To mitigate negative effects in the high-frequency spectrum emission, an original technique is proposed to reduce the dv/dt with lower switching losses compared to classical solutions. The AGD technique is based on a subnanosecond delay feedback loop, which reduces the gate current only during the dv/dt sequence of the switching transients. Hence, the dv/dt and di/dt can be actively controlled separately, and the tradeoff between the dv/dt and EON switching energy is optimized. Since GaN transistors have typical voltage switching times on the order of a few nanoseconds, introducing a feedback loop from the high voltage drain to the gate terminal is quite challenging. In this article, we successfully demonstrate the active gate driving of GaN transistors for both 48 and 400 V applications, with initial open-loop voltage switching times of 3 ns, due to a full CMOS integration. Other methods for dv/dt active control are further discussed. The limits of these methods are explained based on both experimental and simulation results. The AGD showed a clear reduction in the peak dv/dt from -175 to -120 V/ns for the 400 V application.

Low-Frequency Noise Parameter Extraction Method for Single-Layer Graphene FETs

In this paper, a detailed parameter extraction methodology is proposed for low-frequency noise (LFN) in single layer (SL) graphene transistors (GFETs) based on a recently established compact LFN model. Drain current and LFN of two short channel back-gated GFETs (L=300, 100 nm) were measured at lower and higher drain voltages, for a wide range of gate voltages covering the region away from charge neutrality point (CNP) up to CNP at p-type operation region. Current-voltage (IV) and LFN data were also available from a long channel SL top solution-gated (SG) GFET (L=5 um), for both p- and n-type regions near and away CNP. At each of these regimes, the appropriate IV and LFN parameters can be accurately extracted. Regarding LFN, mobility fluctuation effect is dominant at CNP and from there the Hooge parameter aH can be extracted while the carrier number fluctuation contribution which is responsible for the well-known M-shape bias dependence of output noise divided by squared drain current, also observed in our data, makes possible the extraction of the NT parameter related to the number of traps. In the less possible case of a Lambda-shape trend, NT and aH can be extracted simultaneously from the region near CNP. Away from CNP, contact resistance can have a significant contribution to LFN and from there the relevant parameter SDR^2 is defined. The LFN parameters described above can be estimated from the low drain voltage region of operation where the effect of Velocity Saturation (VS) mechanism is negligible. VS effect results in the reduction of LFN at higher drain voltages and from there the IV parameter hOmega which represents the phonon energy and is related to VS effect can be derived both from drain current and LFN data.

Study of Underlapped Finfets Behavior for a Radiation Sensing Purpose

In this paper the electrical characteristics of the Underlapped FinFET transistor is studied for different underlap lengths and underlap oxide material. Disturbs caused by underlap region, such as series resistance effect and the spreading electric field have been evaluated. Besides the underlap length, the impact of oxide permittivity on the on-state current level, fringing fields increasing and on current density was also evaluated. When analyzing the Underlapped FinFET as a radiation sensor, the better sensitivity was obtained for long underlap regions and for transistor biased with high drain voltage. The potential increasing in the underlap region results in on-state current enhancement, which characteristic allows this device present good response for sensing purposes.

Understanding the Role of Temperature and Drain Current Stress in InSnZnO TFTs with Various Active Layer Thicknesses.

Thin-film transistor (TFT) devices composed of metal oxide semiconductors have attracted tremendous research attention globally in recent years. Owing to their ability to offer mobility, metal oxide semiconductor materials can enable high-performance TFTs for next-generation integrated display devices. Nevertheless, further breakthroughs of metal oxide TFTs are mainly obstructed by their long-term variability, the reason for which is not yet fully understood. Herein, TFTs based on InSnZnO (ITZO) with various thicknesses (TITZO) were prepared and their long-term stabilities under test temperatures and drain current stress were investigated. The results indicate that ITZO TFTs exhibit outstanding electrical properties regardless of the TITZO, including a high saturated mobility of over 35 cm2V−1s−1 and sharp subthreshold swing. Note that the transfer and output characteristic curves of the device with a thick TITZO of 100 nm express an abnormal current surge when high gate and drain voltages are exerted, which is attributed to the floating body effect, caused when the imposed electric field induces impact ionization near the drain side. More interestingly, these drain current stress results further suggest that the abnormal shift behavior of the electrical properties of the ITZO TFTs with a TITZO of greater than 75 nm is observed to deteriorate gradually with increasing temperature and drain current bias. This study addresses that such a degradation effect should be restrained for the operation of high-mobility devices.