Electrical instability in short channel organic thin-film transistors induced by lucky-polaron mechanism

Abstract

In this work we study the electrical stability under both gate bias stress and gate and drain bias stress of short channel (L = 5 μm) bottom contact/top gate OTFTs made on flexible substrate with solution-processed organic semiconductor and fluoropolymer gate dielectric. These devices show high field-effect mobility (μ FE > 1 cm 2 V −1 s −1 ) and excellent stability under gate bias stress (bias stress V ds = 0V). However, after prolonged bias stress performed at high drain voltage, V ds , the transfer characteristics show a decreased threshold voltage, degradation of the subthreshold slope and an apparent increase in the field effect mobility. Furthermore, the output characteristics show an asymmetry when measured in forward and reverse mode. These experimental results can be explained considering that the bias stress induces the damage of a small part of the device channel, localized close to the source contact. The analysis of the experimental data through 2D numerical simulations supports this explanation showing that the electrical characteristics after bias stress at high V ds can be reproduced considering the creation of donor-like interface states and trapping of positive charge into the gate dielectric at the source end of the device channel. In order to explain this degradation mechanism, we suggest a new physical model that, assuming holes injection from the source contact into the channel in bounded polarons, envisages the defect creation at the interface near the source end of the channel induced by injection of holes that gained energy from both the high longitudinal electric fields and the polaron dissolution. • Bias stress induced instability in short channel OTFTs is due to small defected channel region at the source contact. • Interface states and charge trapping into the gate dielectric at the source end have been considered in 2D simulations. • A “Lucky-polaron” mechanism well explains the creation of a defected region and carrier injection into the gate dielectric.