High-speed LSI Research Articles

Waveform measurements in high-speed silicon bipolar circuits using a picosecond photoelectron scanning electron microscope

A description is given of a noncontact waveform measurement technique for the characterization of high-speed LSI and VLSI circuits using a picosecond photoelectron scanning electron microscope with 5-ps temporal resolution, 0.1- mu m spatial resolution, and a voltage resolution of 3 mV/ square root Hz. The ability of the technique to measure and monitor the internal waveforms and to resolve the different contributions of the delay in the circuit without any loading effect is demonstrated by its application to the full characterization of sub-100-ps silicon bipolar ECL (emitter-coupled logic) circuits. >

Growth and Characterization of Multilayered Structure of GaAs/Epi-Si/SiO2 /Si Composite

The monolithic integration of GaAs and Si devices is highly attractive for very high speed LSI and optoelectronic integrated circuits. To accomplish this, the epitaxial growth of GaAs films on Si substrates has been successfully realized. However, in the GaAs/Si structure, the conductive nature of the silicon substrate results in a severe transmission line loss [1,2]. To help solve this problem, we suggest to grow GaAs film on SOI (silicon on insulator) substrate for microwave device application. This GaAs/SOI structure will have low transmission line loss and excellent radiation hardness. In this paper, we present some cross-section SEM and TEM data and discuss the transmission line loss and radiation hardness of this multilayered structure.

Device analysis of two‐dimensional electron gas (2DEG)FET

AbstractA one‐dimensional analytical model of 2DEG‐FETs has been developed in which the effect of the source‐gate resistance Rsq and velocity saturation are included. When the electron mobility μ, the electron drift peak velocity Ve, the source‐gate resistance Rsg and the AlGaAs film thickness d are varied, the corresponding transconductance gm and the conductance coefficient K are numerically studied in detail. With the present model, the device characteristics of the “MIS”‐like 2DEG‐FET with a thick n+‐GaAs cap layer and an undoped AlGaAs gate have been analyzed. From the point of application of 2DEG‐FETs to a high speed LSI, the design guideline of the device has been studied. For the device parameters of the gate length Lg = 0.2 μm, the transistor width W = 10 μm, Rsg = 15 Ω, d = 22 mm, μ = 8000 cm2/Vs and Ve = 2 × 107 cm/s, the expected device characteristics are K = 10.0 mA/V2, the sourcegate capacitance Cgs = 10.0 fF, gm = 700 mS/mm and fT = 110 GHz.

Self-aligned complementary bipolar transistors fabricated with a selective-oxidation mask

This paper deals with a self-aligned complementary transistor (vertical n-p-n and vertical p-n-p) structure that is ideal for high-speed and high-accuracy analog bipolar LSI circuits. The device structure consists of a 2-µm epitaxial layer, a non-LOCOS trench isolation buried with polysilicon, and complementary transistors, which are characterized by self-aligned active base and emitter. The key feature lies in the fabrication process, which forms an active base and emitter by ion implantations through a silicon nitride film by the use of an oxidation film that covers an extrinsic base as a mask [1]. The leakage current at the emitter-base junction can be minimized, because the ion-implantation-induced residual defects are confined in the emitter and the extrinsic base regions. The current gains of both transistors (n-p-n and p-n-p) remain constant down to a collector current of I c = 10-9A. The typical distribution of the base-emitter offsets (ΔV BE ) of transistor pairs was 0.2 mV as expressed in the standard deviation = 3σ. The maximum values of f T for n-p-n and p-n-p transistors are 6 and 1.5 GHz, respectively.

The LTD: A fastbus time digitizer for LEP detectors

Abstract This paper describes a high-performance time digitizer for application with detectors requiring a fine time-resolution across a wide dynamic range, as well as multiple event buffering at the front-end level. The flexibility of the device, combined with a relatively low cost, should also make it attractive for a wide range of applications. It is planned to use modern technology in the conception of this unit, e.g. high-speed memories, PALs, and LSI semi-custom ICs (gate arrays).

A 1.5-Mbit/s×128-channel time-switch LSI for digital still picture exchanges

A high-speed time-switch LSI comprising a major part of a 1.5-Mb/s 128-channel digital still-picture switching system has been developed. A pipelined multiplexer architecture which combines a pipelined multiplexer with a shift register is proposed. This design is suitable for high-speed operation, since it consists of repetitive-element circuits with minimum fan-in and fan-out counts. Using conventional 2.5-/spl mu/m CMOS process technology, the measured maximum clock rate and throughput of a time-switch LSI using this architecture are 56 MHz and 224 Mb/s, respectively, under typical conditions. The throughput is about five times as large as that of a standard-type time-switch LSI that uses a RAM fabricated with 2.2-/spl mu/m NMOS process technology.

A fine emitter transistor fabricated by electron-beam lithography for high-speed bipolar LSI's

A highly stable, high-performance bipolar transistor with a 1/4-µm emitter is developed. This is accomplished by using advanced electron-beam (EB) lithography and polysilicon reactive ion etching (RIE). Results show that the minimum emitter width is only 0.2 µm and the emitter width accuracy is ±0.06 µm. In addition, the gate delay is reduced from 190 to 100 ps/gate for 25-stage, three-input ECL circuits. The effects of an ultra-narrow emitter on transistor characteristics are also studied.

Buried p-layer SAINT for very high-speed GaAs LSI's with submicrometer gate length

A new SAINT FET with a depleted p-layer buried under the active layer has been developed in order to make very high-speed GaAs LSI's with submicrometer gate lengths. The p-layer design has successfully suppressed the substrate current that causes the serious short-channel effects in an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> self-aligned (SAINT) MESFET. Since the whole p-layer, formed by Be ion implantation, is depleted by the built-in potential against the upper n-channel layer, it does not lead to a parasitic capacitance increase. The impurity concentration of the player has been limited to optimize operation speed. The alleviation of the short-channel effects combined with the reduction of effective channel thickness has increased the drain current by a factor of about 2 and decreased the propagation delay time of the ring oscillator by a factor of 1.6. A maximum transconductance of 420 mS/mm and a minimum delay time of 9.9 ps/gate have been obtained at room temperature.

A 200 Mbit/s Synchronous TDM Loop Optical LAN Suitable for Multiservice Integration

This paper describes a 200 Mbit/s multiservice optical local area network (LAN) using a synchronous TDM loop structure. The LAN consists of a central supervisory node and multiple service nodes connected by an optical fiber loop. Each service node supports communication channels which have access to allocated time slots in TDM frames continuously circulating on the loop. Multiple independent communication paths of various speeds up to 140 Mbits/s and various modes including point-to-point, ring, and multicast, can be provided between the channels on the loop. The ring will be useful to support ring networks, such as a token ring. The structure of this LAN is quite suitable for integration of multiple services, including video, image, data, and voice, since each service can independently choose its own speed, access method, and mode. In this development, various LSI-based high-speed hardware technologies including compact E/O and O/E modules, GaAs 4 × 4 matrix switch LSI's, and high-speed TDM-processor LSI's, which are versatilely applicable to high-speed LAN's ranging from 100 Mbits/s up to 560 Mbits/s, have been successfully introduced and compact LAN equipment has been obtained. This paper deals mainly with the system and hardware structure of this LAN, together with high-speed hardware technologies. An outline of firmware and network operation, and an application example are also described.

A GaAs 1-kbit static RAM with a shallow recessed-gate structure FET

A novel GaAs FET structure, the shallow recessed-gate structure, has been proposed and applied to a 1-kbit static RAM. In order to decrease the source resistance R s and gate capacitance C g , the shallow n+implanted layer was formed between the gate and source/drain region; then the gate region was slightly recessed. This FET has a high transconductance g m , low source resistance R s , small gate capacitance C g , and small deviation of threshold voltage \part V_{th} , and thus is suitable for high-speed GaAs LSI's. A 1-kbit static RAM has been designed and fabricated applying this FET structure and an access time of 3.8 ns with 38- mW power dissipation has been obtained.

SVG guard-ring Al-Ti-Si schottky diode for high-speed LSI applications

The SVG (shallow V-groove) guardring fabrication technique for Schottky diodes allows a high packing density, a high breakdown voltage, a low leakage and a small junction capacitance to be achieved. By evaporation of a thin titanium film under an aluminum film, the barrier heights of the contacts can be shifted slightly from that of a Al-Si Schottky diode toward thatof a Ti-Si Schottky diode. The barrier height of 0.61 eV was determined by the JF/VF and JF/T2/1/T characteristics. The breakdown voltages of 240 randomly chosen devices were measured at a reverse current level of 1 μA. The high typical breakdown voltage of 26.5 V and its narrow distribution indicate that the field peaking along the periphery of the metal contacts was eliminated by the SVG guard ring. The SVG guard ring blocks the lateral spread of the depletion layer and reduces the junction capacitance to 70% of that of a Schottky diode without guard ring.

GaAs microcircuit contact and interconnect technology

The purpose of this paper is to review the current status of and to discuss key technological issues relative to GaAs integrated circuit contact and interconnect technology. Rapid progress and performance advantages exhibited by GaAs MSI circuits in both ultrahigh speed and low power dissipation has recently provided the motivation for the development of GaAs large-and very-large-scale integration (LSI and VLSI). The complexity, density and small feature size requirements of high speed LSI and VLSI places severe demands on GaAs contact and interconnect technology with respect to yield, reliability and performance. The key device used today in GaAs integrated circuits is the depletion-mode Schottky barrier field effect transistor. Results on the optimization of GaAs field effect transistor Schottky barriers and ohmic contacts using X-ray photoelectron spectroscopy and Auger electron spectroscopy surface analysis techniques in conjunction with thermal reliability studies of various metal systems on GaAs will be presented. The established reliability for GaAs integrated circuits with a goldbased metallization system has been shown to have a mean time to failure of more than 109 h at room temperature. The microcircuit lithography requirements of GaAs LSI and VLSI rely heavily on lift-off and dry etch replication techniques. Several high yield techniques, which have been specifically developed for GaAs, will be described. Finally, recent trends in GaAs device research relative to new non-alloyed contacts and high temperature Schottky barriers will be presented.

A high-speed LSI GaAs 8x8 bit parallel multiplier

Multiplication is frequently the speed-limiting function in digital signal processing systems. High-speed hardware multiplier ICs can therefore greatly enhance the throughput and bandwidth of many digital systems. In this paper, the design, fabrication, and performance of GaAs parallel multipliers are discussed. The largest of these circuits, an 8/spl times/8 bit multiplier, has 1008 gates, and is by far the most complex GaAs IC demonstrated today. This multiplier forms the 16 bit product of two 8 bit input numbers in 5.25 ns. This corresponds to an equivalent gate propagation delay of 150 ps/gate. The power dissipation ranges between 0.6-2 mW/gate.

GaAs Microcircuit Contact and Interconnect Technology

The purpose of this paper is to review the current status of and to discuss key technological issues relative to GaAs integrated circuit contact and interconnect technology. Rapid progress and performance advantages exhibited by GaAs MSI circuits in both ultrahigh speed and low power dissipation has recently provided the motivation for the development of GaAs large-and very-large-scale integration (LSI and VLSI). The complexity, density and small feature size requirements of high speed LSI and VLSI places severe demands on GaAs contact and interconnect technology with respect to yield, reliability and performance.The key device used today in GaAs integrated circuits is the depletion-mode Schottky barrier field effect transistor. Results on the optimization of GaAs field effect transistor Schottky barriers and ohmic contacts using X-ray photoelectron spectroscopy and Auger electron spectroscopy surface analysis techniques in conjunction with thermal reliability studies of various metal systems on GaAs will be presented. The established reliability for GaAs integrated circuits with a goldbased metallization system has been shown to have a mean time to failure of more than 109 h at room temperature.The microcircuit lithography requirements of GaAs LSI and VLSI rely heavily on lift-off and dry etch replication techniques. Several high yield techniques, which have been specifically developed for GaAs, will be described. Finally, recent trends in GaAs device research relative to new non-alloyed contacts and high temperature Schottky barriers will be presented.

High-speed low-power logic ICs using quasi-normally-off GaAs MESFETs

A digital approach, called `low pinchoff-voltage FET logic' (LPFL), is proposed for high-speed LSI circuit applications. It makes use of `quasi-normally-off' GaAs MESFETs, i.e., Schottky-gate devices operating in enhancement model with a pinchoff-voltage ranging between -0.2 and +0.2 V. Such a V/SUB P/ range is about twice that tolerated by conventional normally-off circuits and thus higher fabrication yields can be routinely achieved. Performances which can be achieved with this approach have been tested by means of a single-clocked frequency divider circuit fabricated with MESFETs of 1 /spl mu/m/spl times/20 /spl mu/m gate geometry.

Polyimide liftoff technology for high-density LSI metallization

A new liftoff technology, in which a metallization layer can be deposited at high temperatures, is developed to provide two-level highly packed interconnection metallization. A heat-resistant polymide, PIQ®, is employed as the liftoff layer. The reverse pattern of the metallization is formed by reactive sputter etching of the PIQ layer around a thin Mo mask. After metallization layer deposition, lift-off is carried out by electrolytic etching of the Mo mask, thus removing the layer deposited on PIQ. A higher packing density of interlevel connection is also accomplished by adopting exposed via holes. Utilizing this technology, fine-featured smoothly tapered metallization patterns can be obtained almost irrespective of the underlying topology. The minimum pitches of the first level, second level, and via holes are 5, 7, and 7 µm, respectively. This technology does not appear to be detrimental to bipolar device characteristics. A 4096-bit high-speed bipolar memory LSI with two-level highly packed interconnection metallization was produced experimentally utilizing this liftoff technology.

Wave digital filter hardware structure

A large amount of literature has been published during the last decade on the design of digital filter structures with desirable attributes, such as low round off noise, simple coefficients or ease of implementation. In this paper, the hardware implementation of a structure based on a classical doubly-terminated distributed filter prototype is discussed. This structure has a prarticularly simple form as it is a cascade of identical 1st-order networks. The paper describes a programmable logic design centred on a high-speed bipolar LSI multiplier chip. It is shown that a complete 6th degree wave digital filter with analogue I/O can be implemented on a single S-100 printed-circuit board, and further that the filter can operate at a maximum sampling rate of around 150 kHs. The filter coefficients can be change in the controll program which is also stored in PROM.

Implementation of wave digital filter structures

During the previous few years, many high-speed LSI devices for signal processing have been introduced. This has made the problem of implementing digital filters, and wave digital filters (WDF) in particular, considerably easier. This paper briefly surveys the research carried out on LSI and non-LSI hardware implementations of WDF during the last few years. This paper also describes a modification to earlier work on LSI implementations that enables the realisation of WDF with poles of attenuation.

An Advanced PSA Technology for High-Speed Bipolar LSI

An advanced method for polysilicon self-aligned (PSA) bipolar LSI technology has realized a miniaturized transistor for high performance. By introducing the overlapping structure for double poly-silicon electrodes, the emitter area is reduced to 1/spl mu/m X 3 /spl mu/m and the base junction is reduced to 0.3 /spl mu/m. The CML integrated circuit composed of this transistor has achieved a minimum propagation delay time of 0.29 ns/gate with power dissipation of 1.48 mW/gate. Compared to the conventional PSA method, this technology promises to fabricate higher speed and higher density LSI's.

An advanced PSA technology for high-speed bipolar LSI

An advanced method for polysilicon self-aligned (PSA) bipolar LSI technology has realized a miniaturized transistor for high performance. By introducing the overlapping structure for double polysilicon electrodes, the emitter area is reduced to 1 µm × 3 µm and the base junction is reduced to 0.3 µm. The CML integrated circuit composed of this transistor has achieved a minimum propagation delay time of 0.29 ns/gate with power dissipation of 1.48 mW/gate. Compared to the conventional PSA method, this technology promises to fabricate higher speed and higher density LSI's.