Buried p-layer SAINT for very high-speed GaAs LSI's with submicrometer gate length

Abstract

A new SAINT FET with a depleted p-layer buried under the active layer has been developed in order to make very high-speed GaAs LSI's with submicrometer gate lengths. The p-layer design has successfully suppressed the substrate current that causes the serious short-channel effects in an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> self-aligned (SAINT) MESFET. Since the whole p-layer, formed by Be ion implantation, is depleted by the built-in potential against the upper n-channel layer, it does not lead to a parasitic capacitance increase. The impurity concentration of the player has been limited to optimize operation speed. The alleviation of the short-channel effects combined with the reduction of effective channel thickness has increased the drain current by a factor of about 2 and decreased the propagation delay time of the ring oscillator by a factor of 1.6. A maximum transconductance of 420 mS/mm and a minimum delay time of 9.9 ps/gate have been obtained at room temperature.