High-speed LSI Research Articles

SMS 201 — A powerfull parallel processor with 128 microprocessors

The architecture, organization and application of the SMS multiprocessor system, an MIMD-structure for high-speed numerical computations, are outlined. The now operational SMS 201 with 128 combined microcomputers, each containing an additional arithmetic processing unit, is capable of executing 550 000 floating point operations per second (FLOPS). A similar system, named SMS 80, with a variable number of modules, will be available soon for interested users. A future SMS system using high speed LSI circuits, the newly designed SMS 3, will have a speed of 18 million FLOPS.

Radar: Development and State-of-Art in Hardware

Radar Systems have been in existence for nearly four decades during which period, there have been significant changes and growth in their capability. To provide more reliable systems under different operational conditions, the advances in the field of microwave tubes for transmitter development, low-noise solid-state rf amplifiers for receivers and high-speed digital IC's and LSI devices have been taken full advantage. In this article, the main trends for the radars of the 1980s as well as other trends that will significantly alter the future radars have been brought out.

I2L: Complementing Schottky TTL

In the important area of high-speed digital LSI circuits, I2L represents a higher-density complement to low-power Schottky-TTL technology. Functions requiring a circuit complexity of 500 gates or less probably could be produced economically by use of a standard low-power Schottky process. But for greater-complexity chips that operate over −55 to +125°C, I2L is needed.

Improved feedback ECL gate with low delay-power product for the subnanosecond region

Feedback ECL gates are well suited as basic elements for high-speed LSI circuits. Unfortunately for higher voltage swings, they have a hysteresis which reduces the noise immunity. Here it will be demonstrated theoretically how to remove the hysteresis and how to optimize the transfer characteristic using emitter resistors. For such a gate, a power dissipation of 1.6 mW and a propagation delay time of less than 0.6 ns are evaluated by simulation using the parameters of today's available technologies.