High-speed Architecture Research Articles

PartialHD: Toward Efficient Hyperdimensional Computing by Partial Processing

Hyperdimensional (HD) computing is a brain inspired learning method that is widely employed in resource-constrained applications such as the internet of things (IoT) regarding its lightweight computation. Although HD computing has high efficiency in the IoT applications, it suffers from high computation due to the large vector size. Thus, several studies are proposed to speedup and increase the efficiency of HD computing. In this work, we propose a method to process HD computing called PartialHD. Our method divides a long hypervector into multiple partial vectors, and process each vector separately. In the retraining phase, this method improves accuracy up to 1.93%. Moreover, by employing our proposed method in the retraining and inference, only a few partial vectors participate and this causes the computational overhead reduces in these phases. The evaluation shows that our method processes on average 22.2% and 36.23% of the entire hypervectors with negligible accuracy loss in inference and retraining, respectively. Furthermore, we propose two general architectures (light-weight and high-speed), which accelerate partial vector computations on different FPGA platforms. The result shows that the light-weight architecture can accelerate HD computing on resource-constrained FPGAs such as Artix while the high-speed architecture has 4.72× higher throughput than light-weight architecture.

Secure Approach Using Visual Cryptography

An Image Encryption and Decryption Using AES (Advance Encryption Standard) Algorithm is proposed in this paper. Visual cryptography is the most popular technique attracted various researchers to improve the security level while utilizing the images and videos as encryption key, instead of text which is easy to crack. Visual cryptography computes complex multimedia information which may leads to computational overhead when simple processing techniques and architectures were utilized. So, various researchers had taken over this challenge and trying to resolve while introducing the various high speed techniques and architectures which would make visual cryptography process highly secured and energy efficient. This paper presents an algorithm in which the image is an input to AES Encryption to get the encrypted image and the encrypted image is the input to AES Decryption to get the original image. Keywords: Visual cryptography, security, energy efficient, high speed architecture, accurate prediction outcome, AES algorithm, image encryption, image decryption

Efficient Hardware Implementations of Legendre Symbol Suitable for MPC Applications

Multi-party computation (MPC) allows each peer to take part in the execution of a common function with their private share of data without the need to expose it to other participants. The Legendre symbol is a pseudo-random function (PRF) that is suitable for MPC protocols due to their efficient evaluation process compared to other symmetric primitives. Recently, Legendre-based PRFs have also been employed in the construction of a post-quantum signature scheme, namely LegRoast. In this paper, we propose, to the best of our knowledge, the first hardware implementations for the Legendre symbol by three approaches: 1) low-area, 2) high-speed, and 3) high-frequency. The high-speed architecture outperforms state-of-the-art software implementations, which run on Intel’s Core-i5. Our evaluation results on FPGA show that this architecture reduces the Legendre calculation time by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.56\times $ </tex-math></inline-formula> compared to software implementations on Core-i5. On the other hand, the low-area architecture consumes only 5489 slices on the Artix-7 FPGA and is suitable for resource-constrained devices. Moreover, our ASIC implementation results indicate that the low-area architecture consumes 97.56K gates to implement and requires <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.01~mW$ </tex-math></inline-formula> to operate on 50 MHz. The high-frequency architecture increases the frequency by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.72\times $ </tex-math></inline-formula> over the high-speed architecture and achieves 200 MHz frequency on FPGA.

Content-Addressable Memory System Using a Nanoelectromechanical Memory Switch

Content-addressable memory (CAM) performs a parallel search operation by comparing the search data with all content stored in memory during a single cycle, instead of finding the data using an address. Conventional CAM designs use a dynamic CMOS architecture for high matching speed and high density; however, such implementations require the use of system clocks, and thus, suffer from timing violations and design limitations, such as charge sharing. In this paper, we propose a static-based architecture for a low-power, high-speed binary CAM (BCAM) and ternary CAM (TCAM), using a nanoelectromechanical (NEM) memory switch for nonvolatile data storage. We designed the proposed CAM architectures on a 65 nm process node with a 1.2 V operating voltage. The results of the layout simulation show that the proposed design has up to 23% less propagation delay, three times less matching power, and 9.4 times less area than a conventional design.

Design Space Exploration for High-Speed Implementation of the MISTY1 Block Cipher

This paper proposes 2 × unrolled high-speed architectures of the MISTY1 block cipher for wireless applications including sensor networks and image encryption. Design space exploration is carried out for 8-round MISTY1 utilizing dual-edge trigger (DET) and single-edge trigger (SET) pipelines to analyze the tradeoff w.r.t. speed/area. The design is primarily based on the optimized implementation of lookup tables (LUTs) for MISTY1 and its core transformation functions. The LUTs are designed by logically formulating S9/S7 s-boxes and FI and {FO + 32-bit XOR} functions with the fine placement of pipelines. Highly efficient and high-speed MISTY1 architectures are thus obtained and implemented on the field-programmable gate array (FPGA), Virtex-7, XC7VX690T. The high-speed/very high-speed MISTY1 architectures acquire throughput values of 25.2/43 Gbps covering an area of 1331/1509 CLB slices, respectively. The proposed MISTY1 architecture outperforms all previous MISTY1 implementations indicating high speed with low area achieving high efficiency value. The proposed architecture had higher efficiency values than the existing AES and Camellia architectures. This signifies the optimizations made for proposed high-speed MISTY1 architectures.

An efficient signed digit montgomery modular multiplication algorithm

In this paper, we present a novel radix-2 Montgomery modular multi+d its corresponding architecture for high speed and low ATP implementation. The proposed multiplier, which is based on the Signed Digit Adder(SDA), requires binary input and also generates a modular product in binary form. To speed up radix-2 Montgomery modular multiplication process, we first design a new Simplified SDA(SSDA), dedicated to multipliers based on Non-Adjacent-Form(NAF) methods, which can not only avoid the carry propagation at each addition operation of add-shift loop, but also reduce the addition rounds efficiently. Second, a detecting and skipping mechanism based on the proposed SSDA has been studied to bypass some unnecessary addition rounds which would further reduce the addition rounds. In addition, our proposed Montgomery modular multiplier uses only one-level SDA architecture, and this architecture is also used to both the operand pre-computation and the final format conversion, which lead to a low hardware cost and short critical path delay. At last, we compare the area, the critical path and the cycle number of the proposed multiplier with those of other multipliers based on CSAs and SDAs. Experimental results show that the proposed Montgomery modular multiplier can achieve higher speed(6.9%) and area–time product improvement(19.4%) when compared with previous designs.

Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root

Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root

High-Speed LDPC Decoders Towards 1 Tb/s

Beyond 5G systems are expected to approach 1 Tb/s throughput. This poses a significant challenge to the channel decoder. In this paper, we propose a multi-core architecture based on full row parallel layered LDPC decoder with frame interleaving. Compared with conventional partially parallel layered architectures, the proposed architecture increases the throughput by applying frame interleaving into the pipeline architecture and by using multi-core architectures. Two high rate medium size QC LDPC codes are designed with fast decoding convergence speed for this architecture. Both codes are implemented with single core and multi-core architectures to explore different trade-offs between code design, communication performance and implementation. The four decoders are implemented in 16 nm CMOS FinFET technology with a clock rate of 1 GHz. The placement and routing implementation results show that the single core decoder for the LDPC (1027, 856) code is able to provide 114 Gb/s throughput at maximum 3 iterations with an area of 0.173 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and energy efficiency of 1.56 pJ/bit; the multi-core decoder for the (1032, 860) code is able to provide 860 Gb/s throughput at maximum 2 iterations with an area of 1.48 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and energy efficiency of 3.24 pJ/bit. The multi-core decoder achieves the highest throughput in the literature for medium size (1-2k) LDPC codes. When compared with other state-of-the-art fully parallel high speed architectures, the proposed architectures bring a significant gain both in area efficiency and energy efficiency while keeping the ability to offer flexibility in code rate, number of iterations and early stop.

5G Visible Light Communication - OCDMA Setup using Catenated-OFDM Modulation Method

This paper demonstrates a new high-speed architecture of visible light communication (VLC) system combining with zero cross correlation (ZCC) code of optical code division multiplexing (OCDMA) and novel catenated-OFDM modulation scheme. In order to achieved high spectral efficiency and higher bit rate system for 5G application, we embedded multiband catenated-OFDM modulation technique and OCDMA in VLC design system. Moreover, by employing visible laser diode (VLD) in designing VLC system, we achieved 10 Gbps bit rate at 2.5 dBm input power. We investigate this new combination system design to analyze the bit rate and bit error rate (BER) in 3 m indoor VLC channel propagation.

FPGA Implementation of Particle Filters for Robotic Source Localization

Particle filtering is very reliable in modelling non-Gaussian and non-linear elements of physical systems, which makes it ideal for tracking and localization applications. However, a major drawback of particle filters is their computational complexity, which inhibits their use in real-time applications with conventional CPU or DSP based implementation schemes. The re-sampling step in the particle filters creates a computational bottleneck since it is inherently sequential and cannot be parallelized. This paper proposes a modification to the existing particle filter algorithm, which enables parallel re-sampling and reduces the effect of the re-sampling bottleneck. We then present a high-speed and dedicated hardware architecture incorporating pipe-lining and parallelization design strategies to supplement the modified algorithm and lower the execution time considerably. From an application standpoint, we propose a novel source localization model to estimate the position of a source in a noisy environment using the particle filter algorithm implemented on hardware. The design has been prototyped using Artix-7 field-programmable gate array (FPGA), and resource utilization for the proposed system is presented. Further, we show the execution time and estimation accuracy of the high-speed architecture and observe a significant reduction in computational time. Our implementation of particle filters on FPGA is scalable and modular, with a low execution time of about 5.62 μs for processing 1024 particles (compared to 64 ms on Intel Core i7-7700 CPU with eight cores clocking at 3.60 GHz) and can be deployed for real-time applications.

An Efficient Elliptic-Curve Point Multiplication Architecture for High-Speed Cryptographic Applications

This work presents an efficient high-speed hardware architecture for point multiplication (PM) computation of Elliptic-curve cryptography using binary fields over GF(2163) and GF(2571). The efficiency is achieved by reducing: (1) the time required for one PM computation and (2) the total number of required clock cycles. The required computational time for one PM computation is reduced by incorporating two modular multipliers (connected in parallel), a serially connected adder after multipliers and two serially connected squarer units (one after the first multiplier and another after the adder). To optimize the total number of required clock cycles, the point addition and point double instructions for PM computation of the Montgomery algorithm are re-structured. The implementation results after place-and-route over GF(2163) and GF(2571) on a Xilinx Virtex-7 FPGA device reveal that the proposed high-speed architecture is well-suited for the network-related applications, where millions of heterogeneous devices want to connect with the unsecured internet to reach an acceptable performance.

Novel 4:2 Approximate Compressor Designs for Multimedia and Neural Network Applications

Low power dissipation in approximate arithmetic circuits has laid the foundation for area-efficient computational units for error resilient applications like image and signal processing. This paper proposes two novel low power high speed architectures for approximate 4:2 compressor that can be employed in multipliers for partial product summation. The two designs presented ([Formula: see text] and [Formula: see text]) have Error Distance (ED) of [Formula: see text] and Error Rate (ER) of 25%. The proposed [Formula: see text] and [Formula: see text] are able to achieve reduction in power and delay by (62.50%, 47.67%) and (83.13%, 60.20%), respectively, in comparison with the exact 4:2 compressor. To verify the effectiveness of the design, the proposed architectures are used to implement [Formula: see text] Dadda multiplier. The equal number of errors in positive and negative directions in the proposed designs aid in reducing the Mean Error Distance (MED) and Mean Relative Error Distance (MRED) of the multiplier. Multiplication of images and two-level decomposition of 2D Haar wavelets are implemented using the designed Dadda multiplier. The efficiency of the image processing applications is measured in terms of Mean Structural Similarity (MSSIM) index and Peak Signal-to-Noise Ratio (PSNR) and an average of 0.98 and 35[Formula: see text]dB, respectively, is obtained, which are in the acceptable range. In addition, a Convolutional Neural Network (CNN)-based LeNet-1 Handwritten Digit Recognition System (HDRS) is implemented using the proposed compressor-based multipliers. The proposed compressor-based architectures are able to achieve an average accuracy of 96.23%.

An Efficient Hardware Architecture with Adjustable Precision and Extensible Range to Implement Sigmoid and Tanh Functions

The efficient and precise hardware implementations of tanh and sigmoid functions play an important role in various neural network algorithms. Different applications have different requirements for accuracy. However, it is difficult for traditional methods to achieve adjustable precision. Therefore, we propose an efficient-hardware, adjustable-precision and high-speed architecture to implement them for the first time. Firstly, we present two methods to implement sigmoid and tanh functions. One is based on the rotation mode of hyperbolic CORDIC and the vector mode of linear CORDIC (called RHC-VLC), another is based on the carry-save method and the vector mode of linear CORDIC (called CSM-VLC). We validate the two methods by MATLAB and RTL implementations. Synthesized under the TSMC 40 nm CMOS technology, we find that a special case AR∣VR(3,0), based on RHC-VLC method, has the area of 4290.98 μm2 and the power of 1.69 mW at the frequency of 1.5 GHz. However, under the same frequency, AR∣VC(3) (a special case based on CSM-VLC method) costs 3196.36 μm2 area and 1.38 mW power. They are both superior to existing methods for implementing such an architecture with adjustable precision.

Improved throughput of Elliptic Curve Digital Signature Algorithm (ECDSA) processor implementation over Koblitz curve k-163 on Field Programmable Gate Array (FPGA)

The widespread use of the Internet of things (IoT) in different aspects of an individual’s life like banking, wireless intelligent devices and smartphones has led to new security and performance challenges under restricted resources. The Elliptic Curve Digital Signature Algorithm (ECDSA) is the most suitable choice for the environments due to the smaller size of the encryption key and changeable security related parameters. However, major performance metrics such as area, power, latency and throughput are still customisable and based on the design requirements of the device.&#x0D; The present paper puts forward an enhancement for the throughput performance metric by proposing a more efficient design for the hardware implementation of ECDSA. The design raised the throughput to 0.08207 Mbit/s, leading to an increase of 6.95% from the existing design. It also includes the design and implementation of the Universal Asynchronous Receiver Transmitter (UART) module. The present work is based on a 163-bit key-size over Koblitz curve k-163 and secure hash function SHA-1. A serial module for the underlying modular layer, high-speed architecture of Koblitz point addition and Koblitz point multiplication have been considered in this work, in addition to utilising the carry-save-multiplier, modular adder-subtractor and Extended Euclidean module for ECDSA protocols. All modules are designed using VHDL and implemented on the platform Virtex5 xc5vlx155t-3ff1738. Signature generation requires 0.55360ms, while its validation consumes 1.10947288ms. Thus, the total time required to complete both processes is equal to 1.66ms and the maximum frequency is approximately 83.477MHZ, consuming a power of 99mW with the efficiency approaching 3.39 * 10-6.

High-Speed Architecture for Successive Cancellation Decoder With Split-g Node Block

Polar codes are one of the recently developed error correcting codes, and they are popular due to their capacity achieving nature. The architecture of the successive cancellation (SC) decoder algorithm is composed of a recursive processing element (PE). The PE comprises various blocks that include signed adder, subtractor, comparator, multiplexers, and few logic gates. Therefore, the latency of the PE is a primary concern. Hence, a high-speed architecture for implementing the SC decoding algorithm for polar codes is proposed. In the proposed work, a novel restructuring of the 2bit-SC (2b-SC) precomputation decoder architecture is carried out to reduce the latency by 20% while reducing the hardware complexity. Compared to the 2b-SC precomputation decoder, the proposed architecture also has 19% increased throughput for (1024, 512) polar codes with 45% reduction in the gate count.

A new fast and efficient 2-D median filter architecture

Existing architectures for the median filter are based on sorting algorithm where comparators are used in serial. This paper proposes a new high-speed architecture of two dimensional (2-D) median filter where compare and select modules are used in parallel to sort the incoming numbers. The hardware implementation results show that the proposed architecture (PA) operates at 26% and 34% higher frequency in Virtex 4 and Virtex 7 FPGA device, respectively, in comparison with the architectures reported. The PA is synthesized using the RTL Compiler of Cadence along with Faraday 180 nm standard cell library. The maximum operating frequency of the PA is 1.06 GHz with a total gate count of 917. The complete chip layout has been done using the SoC encounter tool. The area of the final chip is 0.13928 mm $$^2$$ with a power consumption of 0.168 mW analysed using prime-power.

Multi-Hop Relay Based Free Space Optical Communication Link for Delivering Medical Services in Remote Areas

Free Space Optical (FSO) communication links are although extremely vulnerable to atmospheric adversities, multi-hop relay transmission can however, significantly improve the link performance and reliability. This paper proposes 120 Gbps DP-16 QAM modulated multi-hop serial FSO link with coherent reception for delivering medical consultation services in remote and isolated locations. Considering the current situation wherein pandemic of highly infectious nature, COVID-19 has affected millions of people globally; doctors can use the proposed high-speed architecture for “contact-less” supervision of quarantined patients and suspects through video conferencing. Each relay terminal uses an all-optical amplify-and-forward technique with Erbium-doped fiber amplifier (EDFA) and gain optimization as its core elements. As a possible last-mile application for delivering medical/health care services, the proposed link has been evaluated for reliability by exposing the link to varied atmospheric conditions. Our results reveal that at target BER of $10^{-5}$ , the useful communication link range of proposed multi-hop link increments by 1.8 kms as compared to direct link that operates under similar channel conditions. Furthermore, compared to results from recent literature on high-speed FSO [30], the proposed link shows enhancement in link range by approximately 0.7 km. The analysis also reveals that as the number of relay nodes increases, the error performance of the link for different atmospheric conditions approaches a state of convergence.

Hybrid parallel adder for 3X multiple generation in radix-8 booth encoding using fast carry tree structure

PurposeIn most commercial processors, enhancing the speed of multiplication using radix-8 booth encoding is the preferred option. In radix-8 architecture, the 3X(= 2X + X) multiple generation is a major bottleneck. This paper aims to propose a parallel implementation scheme recognizing the symmetry in the carry recurrence equations of 3X multiples. The proposed architecture evaluates the odd (H) and even (K) carry signals separately. As prefix tree structure offers fast carry propagation, the parallel implementation is based on a hybrid style of two popular prefix architectures.Design/methodology/approachThe performance of the proposed architecture is evaluated using Cadence TSMC 180 nm library. A comparison of performance parameters with other architectures has been carried out to highlight the architectural advantages of the proposed architecture.FindingsA comparison of performance parameters with others shows that the proposed architecture has a reduced critical path and a commensurate improvement in delay for a bit width of 64. It is shown that up to 32 bits, this parallel architecture has a superior performance and would be the appropriate choice for Application Specific Integrated Circuit (ASIC) implementation. It has also been suggested that higher-order bit widths could be implemented using a modular arrangement.Originality/valueThis paper proposes a new parallel architecture for hard multiple (3X) generation in Radix-8 Booth encoding. As the multiplication is the key operation in digital signal processors, this type of high-speed architectures gains importance in the future processor design. Defence applications such as target finding and multiple target recognitions and image processing applications necessitate this type of high-speed multipliers. Also, it is appropriate for the ASIC implementation. The authors would like to mention that this paper is not yet published anywhere, and it is the research paper of Dr R. Nirmaladevi.

Low power noise immune node voltage comparison keeper design for high speed architectures

The demand for high speed and area minimization has directed the designers towards dynamic CMOS logic design. The domino logic is one of the famous logic in dynamic CMOS logic. The designer needs to compromise the circuit speed and power consumption to reduce the impact of noise in domino logic circuit design. In this work, low power domino logic circuit is proposed to decrease power consumption with improvement in noise immunity. The low power consumption is achieved at the cost small sacrifice in delay. However, the proposed logic circuit has attained better Power Delay Product (PDP) as compared to existing noise tolerant circuits. The experimental simulation results shows the proposed logic exhibit 3.4% power reduction when compared with the low power domino logic circuit [10] for two input OR gates. The proposed logic had a little compromise with delay in the existing logics. However, the Power Delay Product (PDP) of proposed logic circuit has reduced as compared to existing techniques. The proposed logic also provides the better improvement in noise immunity parameters such as UNG and ANTE as compared to the existing logics. The proposed logic circuit based application circuit such as 4:1 multiplexer also provides better improvement in case of power consumption and noise immunity.

VLSI implementation of distributed arithmetic based block adaptive finite impulse response filter

In this paper, an efficient VLSI architecture of distributed arithmetic (DA) based block least mean square (BLMS) adaptive finite impulse response (ADFIR) filter implementation with parallel processing is proposed. In DA scheme, the filter partial products are precomputed and saved in lookup table (LUT) and then by using shift and accumulation operations filtering can be done. To improve the efficiency, a high level of parallelism is incorporated in the design of variable coefficient ADFIR filter. The parallel LUT followed by shift-accumulate operations replaces multiply and accumulate (MAC) operations. By using BLMS algorithm in ADFIR filter with block length P gives P times fast throughput. Since memory reuse concept is used, the design requires less number of registers to calculate output vector and coefficient increment vector. The proposed design is implemented on FPGA. The implementation results indicate that the proposed design is a low power and high speed architecture. The proposed structure provides 47.4% less power and 22.7% less delay when compared to existing designs.