An efficient signed digit montgomery modular multiplication algorithm

Abstract

In this paper, we present a novel radix-2 Montgomery modular multi+d its corresponding architecture for high speed and low ATP implementation. The proposed multiplier, which is based on the Signed Digit Adder(SDA), requires binary input and also generates a modular product in binary form. To speed up radix-2 Montgomery modular multiplication process, we first design a new Simplified SDA(SSDA), dedicated to multipliers based on Non-Adjacent-Form(NAF) methods, which can not only avoid the carry propagation at each addition operation of add-shift loop, but also reduce the addition rounds efficiently. Second, a detecting and skipping mechanism based on the proposed SSDA has been studied to bypass some unnecessary addition rounds which would further reduce the addition rounds. In addition, our proposed Montgomery modular multiplier uses only one-level SDA architecture, and this architecture is also used to both the operand pre-computation and the final format conversion, which lead to a low hardware cost and short critical path delay. At last, we compare the area, the critical path and the cycle number of the proposed multiplier with those of other multipliers based on CSAs and SDAs. Experimental results show that the proposed Montgomery modular multiplier can achieve higher speed(6.9%) and area–time product improvement(19.4%) when compared with previous designs.