Abstract

This work presents an efficient high-speed hardware architecture for point multiplication (PM) computation of Elliptic-curve cryptography using binary fields over GF(2163) and GF(2571). The efficiency is achieved by reducing: (1) the time required for one PM computation and (2) the total number of required clock cycles. The required computational time for one PM computation is reduced by incorporating two modular multipliers (connected in parallel), a serially connected adder after multipliers and two serially connected squarer units (one after the first multiplier and another after the adder). To optimize the total number of required clock cycles, the point addition and point double instructions for PM computation of the Montgomery algorithm are re-structured. The implementation results after place-and-route over GF(2163) and GF(2571) on a Xilinx Virtex-7 FPGA device reveal that the proposed high-speed architecture is well-suited for the network-related applications, where millions of heterogeneous devices want to connect with the unsecured internet to reach an acceptable performance.

Highlights

  • Information security aims to optimally use a wide variety of cryptographic algorithms in network related applications such as network servers

  • We provide an efficient scheduling of point addition (PA) and point doubling (PD) instructions for point multiplication (PM)

  • If PM contains a base point P and a large integer k of the size of the underlying field, PM is the addition of k copies of point P, i.e., Q = k × ( P + P + · · · + P), where Q is a new point on the defined elliptic-curve

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Summary

Introduction

Information security aims to optimally use a wide variety of cryptographic algorithms in network related applications such as network servers In this context, two variants of cryptographic algorithms, i.e., symmetric and asymmetric, are commonly involved. The security strength of ECC and RSA depends on solving the discrete logarithms and large integer primes, respectively. Both of these asymmetric algorithms are not completely comparable to each other—neither historically nor in terms of performance and age. The two commonly used options for the point representation are polynomial basis and normal basis It has been observed in [3,7,8,9] that the binary field is generally preferred due to efficient hardware implementations of arithmetic operations. In many ongoing internet and network applications such as Secure Socket Layer (SSL), Transport Layer Security (TLS), network servers and IPsec protocols, a high-speed computation of arithmetic operations related to ECC is critical [20]

Existing High-Speed State-of-the-Art Implementations
Limitations in the Existing Solutions
Our Contributions
Background
Instructions Parallelization for Point Addition
Instructions Parallelization for Point Doubling
Overall Decrease in Total Number of Clock Cycles
Proposed High-Speed Elliptic-Curve Point Multiplication Architecture
Memory Unit
Structure of the Data Path
Implementation of Modular Operators
Control Unit
Implementation Results and Comparisons
Comparison with State-of-the-Art Solutions
Comparison over Virtex-5
Comparison over Virtex-7
Conclusions
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