Abstract
In this paper, we propose a novel parallel architecture for fast hardware implementation of elliptic curve point multiplication (ECPM), which is the key operation of an elliptic curve cryptography processor. The point multiplication over binary fields is synthesized on both FPGA and ASIC technology by designing fast elliptic curve group operations in Jacobian projective coordinates. A novel combined point doubling and point addition (PDPA) architecture is proposed for group operations to achieve high speed and low hardware requirements for ECPM. It has been implemented over the binary field which is recommended by the National Institute of Standards and Technology (NIST). The proposed ECPM supports two Koblitz and random curves for the key sizes 233 and 163 bits. For group operations, a finite-field arithmetic operation, e.g. multiplication, is designed on a polynomial basis. The delay of a 233-bit point multiplication is only 3.05 and 3.56 μs, in a Xilinx Virtex-7 FPGA, for Koblitz and random curves, respectively, and 0.81 μs in an ASIC 65-nm technology, which are the fastest hardware implementation results reported in the literature to date. In addition, a 163-bit point multiplication is also implemented in FPGA and ASIC for fair comparison which takes around 0.33 and 0.46 μs, respectively. The area-time product of the proposed point multiplication is very low compared to similar designs. The performance () and Area × Time × Energy (ATE) product of the proposed design are far better than the most significant studies found in the literature.
Highlights
With the swift growth of secure transactions over the network, the demand for cryptography to ensure security has increased rapidly in recent times
Contributions: This paper proposes a parallel hardware architecture for point multiplication using combined point doubling and point addition (PDPA) in Jacobian projective coordinates
To provide efficient point multiplication, a novel combined group operation (PDPA) is designed which performs the PD and PA operations in parallel, aimed at reducing the number of levels and logic stages needed with separate PD and PA operations
Summary
With the swift growth of secure transactions over the network, the demand for cryptography to ensure security has increased rapidly in recent times. Numerous FPGA implementations of point multiplication over a binary field GF (2m) have been proposed in the literature, e.g. Most of the implementations of ECPM over GF(2163) are not secure based on today’s security level requirements For this reason, a 233-bit point multiplication is implemented both in FPGA and ASIC. An FPGA implementation of ECPM based on the Montgomery ladder method over binary fields is proposed in [9] and [21] They designed the point multiplication using elliptic curve point addition (PA) and point doubling (PD). Various techniques are introduced, using either FPGA or ASIC implementation, to improve the performance of point multiplication, such as algorithm optimization and improved finite-field arithmetic architectures. A parallel hardware architecture using separate group operations (PD and PA) for the ECPM is designed and implemented, and compared.
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